From patchwork Mon May 7 16:52:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 10384511 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9357660353 for ; Mon, 7 May 2018 16:52:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 92CA228825 for ; Mon, 7 May 2018 16:52:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 87B1B28864; Mon, 7 May 2018 16:52:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1D99328825 for ; Mon, 7 May 2018 16:52:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4DC6F6E426; Mon, 7 May 2018 16:52:40 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9CA916E41D for ; Mon, 7 May 2018 16:52:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 May 2018 09:52:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,374,1520924400"; d="scan'208";a="43866040" Received: from rosetta.fi.intel.com ([10.237.72.186]) by fmsmga002.fm.intel.com with ESMTP; 07 May 2018 09:52:36 -0700 Received: by rosetta.fi.intel.com (Postfix, from userid 1000) id 851328402F4; Mon, 7 May 2018 19:52:26 +0300 (EEST) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Mon, 7 May 2018 19:52:19 +0300 Message-Id: <20180507165222.17009-2-mika.kuoppala@linux.intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180507165222.17009-1-mika.kuoppala@linux.intel.com> References: <20180507165222.17009-1-mika.kuoppala@linux.intel.com> Subject: [Intel-gfx] [PATCH 2/5] drm/i915/gtt: Combine marking engines dirty with wmb X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Auld MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP It is a common pattern to mark the tlbs dirty along with flushing the writes. Introduce gen6_ppgtt_invalidate for this. Cc: Chris Wilson Cc: Matthew Auld Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 2963d3d71729..b162617afe18 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -108,6 +108,21 @@ static int i915_get_ggtt_vma_pages(struct i915_vma *vma); +static void gen6_ppgtt_invalidate(struct i915_address_space * const vm) +{ + struct i915_hw_ppgtt * const ppgtt = i915_vm_to_ppgtt(vm); + + /* PDE TLBs are a pain to invalidate on GEN8+. When we modify + * the page table structures, we mark them dirty so that + * context switching/execlist queuing code takes extra steps + * to ensure that tlbs are flushed. + */ + ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask; + + /* Flush write combining buffer */ + wmb(); +} + static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv) { /* Flush write combining buffer */ @@ -814,15 +829,6 @@ static int gen8_mm_switch_4lvl(struct i915_hw_ppgtt *ppgtt, return gen8_write_pdp(rq, 0, px_dma(&ppgtt->pml4)); } -/* PDE TLBs are a pain to invalidate on GEN8+. When we modify - * the page table structures, we mark them dirty so that - * context switching/execlist queuing code takes extra steps - * to ensure that tlbs are flushed. - */ -static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) -{ - ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask; -} /* Removes entries from a single page table, releasing it if it's empty. * Caller can use the return value to update higher-level entries. @@ -1398,7 +1404,7 @@ static int gen8_ppgtt_alloc_pdp(struct i915_address_space *vm, gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe); GEM_BUG_ON(pdp->used_pdpes > i915_pdpes_per_pdp(vm)); - mark_tlbs_dirty(i915_vm_to_ppgtt(vm)); + gen6_ppgtt_invalidate(vm); } ret = gen8_ppgtt_alloc_pd(vm, pd, start, length); @@ -1724,8 +1730,7 @@ static void gen6_write_page_range(struct i915_hw_ppgtt *ppgtt, gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) gen6_write_pde(ppgtt, pde, pt); - mark_tlbs_dirty(ppgtt); - wmb(); + gen6_ppgtt_invalidate(&ppgtt->base); } static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt) @@ -1939,10 +1944,8 @@ static int gen6_alloc_va_range(struct i915_address_space *vm, } } - if (flush) { - mark_tlbs_dirty(ppgtt); - wmb(); - } + if (flush) + gen6_ppgtt_invalidate(vm); return 0;