diff mbox

[4/5] drm/i915/gtt: Flush write combining buffer on insert entries

Message ID 20180507165222.17009-4-mika.kuoppala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Mika Kuoppala May 7, 2018, 4:52 p.m. UTC
We could be using write combining map through which we insert
our ptes. Make sure to flush the write combining buffer
after the writes.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Chris Wilson May 7, 2018, 7:38 p.m. UTC | #1
Quoting Mika Kuoppala (2018-05-07 17:52:21)
> We could be using write combining map through which we insert
> our ptes. Make sure to flush the write combining buffer
> after the writes.

"Could?" We do flush the ppgtt before execution, and the ppgtt is only
used by execution.
-Chris
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6434ebe8c033..dcac8bd604ab 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1077,6 +1077,9 @@  static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
 				      cache_level);
 
 	vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
+
+	/* Flush write combining buffer */
+	wmb();
 }
 
 static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
@@ -1196,6 +1199,9 @@  static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
 
 		vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
 	}
+
+	/* Flush write combining buffer */
+	wmb();
 }
 
 static void gen8_free_page_tables(struct i915_address_space *vm,