From patchwork Wed May 9 14:28:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 10389683 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A9CEA60236 for ; Wed, 9 May 2018 14:28:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E6D4E28674 for ; Wed, 9 May 2018 14:28:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DB7AA286A9; Wed, 9 May 2018 14:28:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 85CDA28674 for ; Wed, 9 May 2018 14:28:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D2BD06ED28; Wed, 9 May 2018 14:28:15 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id 24CA26ED28 for ; Wed, 9 May 2018 14:28:13 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 11646612-1500050 for multiple; Wed, 09 May 2018 15:28:07 +0100 Received: by haswell.alporthouse.com (sSMTP sendmail emulation); Wed, 09 May 2018 15:28:09 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Wed, 9 May 2018 15:28:00 +0100 Message-Id: <20180509142801.28130-4-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180509142801.28130-1-chris@chris-wilson.co.uk> References: <20180509142801.28130-1-chris@chris-wilson.co.uk> X-Originating-IP: 78.156.65.138 X-Country: code=GB country="United Kingdom" ip=78.156.65.138 Subject: [Intel-gfx] [PATCH 4/5] drm/i915/execlists: Direct submission from irq handler X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Continuing the theme of bypassing ksoftirqd latency, also first try to directly submit from the CS interrupt handler to clear the ELSP and queue the next. In the past, we have been hesitant to do this as the context switch processing has been quite heavy, requiring forcewaked mmio. However, as we now can read the GPU state from the cacheable HWSP, it is relatively cheap! v2: Explain why we test_bit(IRQ_EXECLIST) after doing notify_ring (it's because the notify_ring() may itself trigger direct submission clearing the bit) Suggested-by: Tvrtko Ursulin Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_irq.c | 21 ++++++++++++++------- drivers/gpu/drm/i915/i915_tasklet.h | 21 +++++++++++++++++++++ drivers/gpu/drm/i915/intel_guc_submission.c | 2 ++ 3 files changed, 37 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index f8aff5a5aa83..e1b3a7575fe7 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1465,19 +1465,26 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir) struct intel_engine_execlists * const execlists = &engine->execlists; bool tasklet = false; - if (iir & GT_CONTEXT_SWITCH_INTERRUPT) { - if (READ_ONCE(engine->execlists.active)) - tasklet = !test_and_set_bit(ENGINE_IRQ_EXECLIST, - &engine->irq_posted); - } + if (iir & GT_CONTEXT_SWITCH_INTERRUPT && READ_ONCE(execlists->active)) + tasklet = !test_and_set_bit(ENGINE_IRQ_EXECLIST, + &engine->irq_posted); if (iir & GT_RENDER_USER_INTERRUPT) { notify_ring(engine); - tasklet |= USES_GUC_SUBMISSION(engine->i915); + /* + * notify_ring() may trigger direct submission onto this + * engine, clearing the ENGINE_IRQ_EXECLIST bit. In that + * case, we don't want to resubmit and so clear the tasklet + * boolean. GuC never sets the ENGINE_IRQ_EXECLIST bit and + * so when using the GuC this equates to an unconditional + * setting of tasklet to true. + */ + if (!test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) + tasklet = USES_GUC_SUBMISSION(engine->i915); } if (tasklet) - i915_tasklet_schedule(&execlists->tasklet); + i915_tasklet(&execlists->tasklet); } static void gen8_gt_irq_ack(struct drm_i915_private *i915, diff --git a/drivers/gpu/drm/i915/i915_tasklet.h b/drivers/gpu/drm/i915/i915_tasklet.h index 99e2fa2241ba..c532282551b7 100644 --- a/drivers/gpu/drm/i915/i915_tasklet.h +++ b/drivers/gpu/drm/i915/i915_tasklet.h @@ -99,4 +99,25 @@ static inline void i915_tasklet_run(const struct i915_tasklet *t) __i915_tasklet_run(t); } +static inline bool i915_tasklet_try(struct i915_tasklet *t) +{ + if (unlikely(!tasklet_trylock(&t->base))) + return false; + + if (i915_tasklet_is_enabled(t)) + i915_tasklet_run(t); + + tasklet_unlock(&t->base); + return true; +} + +static inline void i915_tasklet(struct i915_tasklet *t) +{ + if (!i915_tasklet_is_enabled(t)) /* GPU reset active */ + return; + + if (!i915_tasklet_try(t)) + i915_tasklet_schedule(t); +} + #endif /* _I915_TASKLET_H_ */ diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index f2ded1796523..4e09abf7e206 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -780,6 +780,8 @@ static void guc_submission_tasklet(unsigned long data) struct execlist_port *port = execlists->port; struct i915_request *rq; + clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); + rq = port_request(port); while (rq && i915_request_completed(rq)) { trace_i915_request_out(rq);