From patchwork Wed May 9 17:48:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lionel Landwerlin X-Patchwork-Id: 10390501 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C8C05602C2 for ; Wed, 9 May 2018 17:49:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B86B9285D4 for ; Wed, 9 May 2018 17:49:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AD017285D9; Wed, 9 May 2018 17:49:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 65EF2285D4 for ; Wed, 9 May 2018 17:49:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B49AC6ED6F; Wed, 9 May 2018 17:49:04 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id BEC016ED68 for ; Wed, 9 May 2018 17:49:02 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 May 2018 10:49:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,382,1520924400"; d="scan'208";a="39960321" Received: from delly.ld.intel.com ([10.103.238.201]) by orsmga008.jf.intel.com with ESMTP; 09 May 2018 10:49:01 -0700 From: Lionel Landwerlin To: intel-gfx@lists.freedesktop.org Date: Wed, 9 May 2018 18:48:47 +0100 Message-Id: <20180509174851.13847-5-lionel.g.landwerlin@intel.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180509174851.13847-1-lionel.g.landwerlin@intel.com> References: <20180509174851.13847-1-lionel.g.landwerlin@intel.com> Subject: [Intel-gfx] [PATCH v4 4/8] drm/i915: add new pipe control helper for mmio writes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP We'll use those helpers in the following commits. It's a good thing to have them around as they need to apply a particular workaround on Skylake. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/intel_lrc.c | 34 +++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++++ 2 files changed, 39 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index e754e9d112a5..6fe0d668c023 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2151,6 +2151,40 @@ static void gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs) } static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS; +u32 gen8_lri_pipe_control_len(struct drm_i915_private *dev_priv) +{ + return IS_SKYLAKE(dev_priv) ? (7) : 5; +} + +u32 *gen8_emit_lri_pipe_control(struct drm_i915_private *dev_priv, + u32 *cs, u32 flags, u32 offset, + u32 value) +{ + /* + * Project: SKL + * + * "PIPECONTROL command with "Command Streamer Stall Enable" must be + * programmed prior to programming a PIPECONTROL command with LRI + * Post Sync Operation in GPGPU mode of operation (i.e when + * PIPELINE_SELECT command is set to GPGPU mode of operation)." + * + * Since the mode of operation is selected from userspace, we apply + * this workaround all the time one SKL. + */ + if (IS_SKYLAKE(dev_priv)) { + *cs++ = GFX_OP_PIPE_CONTROL(2); + *cs++ = PIPE_CONTROL_CS_STALL; + } + + *cs++ = GFX_OP_PIPE_CONTROL(5); + *cs++ = PIPE_CONTROL_MMIO_WRITE | flags; + *cs++ = offset; + *cs++ = 0; + *cs++ = value; + + return cs; +} + static int gen8_init_rcs_context(struct i915_request *rq) { int ret; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 010750e8ee44..aa643a1d69db 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -1042,6 +1042,11 @@ gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset) return cs; } +u32 gen8_lri_pipe_control_len(struct drm_i915_private *dev_priv); +u32 *gen8_emit_lri_pipe_control(struct drm_i915_private *dev_priv, + u32 *cs, u32 flags, u32 offset, + u32 value); + bool intel_engine_is_idle(struct intel_engine_cs *engine); bool intel_engines_are_idle(struct drm_i915_private *dev_priv);