| Message ID | 20180511195145.3829-5-dhinakaran.pandiyan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, 2018-05-11 at 12:51 -0700, Dhinakaran Pandiyan wrote: > Noticed that we assume the best case of 0 latency when the DPCD read > fails, reasonable pessimism is safer. > > eDP spec does say that if latency is greater than 8, the panel > supplier needs to provide it. I didn't see anything specific in the > VBT > for this, so let's go with 8 frames as a fallback. > > Cc: Jose Roberto de Souza <jose.souza@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > --- > drivers/gpu/drm/i915/intel_psr.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > index 381dbdbf30f4..b4a4f5d3a2bb 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -223,13 +223,13 @@ static bool intel_dp_get_alpm_status(struct > intel_dp *intel_dp) > > static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) > { > - u8 val = 0; > + u8 val = 8; /* assume the worst if we can't read the value > */ > > if (drm_dp_dpcd_readb(&intel_dp->aux, > DP_SYNCHRONIZATION_LATENCY_IN_SINK, > &val) == 1) > val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; > else > - DRM_ERROR("Unable to get sink synchronization > latency\n"); > + DRM_DEBUG_KMS("Unable to get sink synchronization > latency, assuming 8 frames\n"); Maybe have this at least as a warning. > return val; > } >
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 381dbdbf30f4..b4a4f5d3a2bb 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -223,13 +223,13 @@ static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) { - u8 val = 0; + u8 val = 8; /* assume the worst if we can't read the value */ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; else - DRM_ERROR("Unable to get sink synchronization latency\n"); + DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n"); return val; }
Noticed that we assume the best case of 0 latency when the DPCD read fails, reasonable pessimism is safer. eDP spec does say that if latency is greater than 8, the panel supplier needs to provide it. I didn't see anything specific in the VBT for this, so let's go with 8 frames as a fallback. Cc: Jose Roberto de Souza <jose.souza@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> --- drivers/gpu/drm/i915/intel_psr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)