From patchwork Mon May 14 15:55:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lionel Landwerlin X-Patchwork-Id: 10398827 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6F1B6601E7 for ; Mon, 14 May 2018 15:56:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6006728173 for ; Mon, 14 May 2018 15:56:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5457928382; Mon, 14 May 2018 15:56:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id F1A2A28173 for ; Mon, 14 May 2018 15:56:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 34BC86E0BC; Mon, 14 May 2018 15:56:16 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 393156E0AD for ; Mon, 14 May 2018 15:56:11 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 May 2018 08:56:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,400,1520924400"; d="scan'208";a="228352242" Received: from delly.ld.intel.com ([10.103.238.202]) by fmsmga005.fm.intel.com with ESMTP; 14 May 2018 08:56:10 -0700 From: Lionel Landwerlin To: intel-gfx@lists.freedesktop.org Date: Mon, 14 May 2018 16:55:59 +0100 Message-Id: <20180514155600.16521-7-lionel.g.landwerlin@intel.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514155600.16521-1-lionel.g.landwerlin@intel.com> References: <20180514155600.16521-1-lionel.g.landwerlin@intel.com> Subject: [Intel-gfx] [PATCH v5 6/7] drm/i915: count powergating transitions per engine X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This can be used to monitor the number of powergating transition changes for a particular workload. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++ drivers/gpu/drm/i915/intel_lrc.c | 16 +++++++++++++++- drivers/gpu/drm/i915/intel_ringbuffer.h | 12 ++++++++++++ 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 9f86e40f22a7..ab3ab80daf62 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -494,6 +494,7 @@ void intel_engine_setup_common(struct intel_engine_cs *engine) i915_timeline_init(engine->i915, &engine->timeline, engine->name); memset(&engine->last_sseu, 0, sizeof(engine->last_sseu)); + atomic_set(&engine->sseu_transitions, 0); intel_engine_init_execlist(engine); intel_engine_init_hangcheck(engine); @@ -1428,6 +1429,8 @@ void intel_engine_dump(struct intel_engine_cs *engine, hexdump(m, engine->status_page.page_addr, PAGE_SIZE); drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine))); + + drm_printf(m, "Powergating transitions: %u\n", atomic_read(&engine->sseu_transitions)); } static u8 user_class_map[] = { diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 0e93ad90d039..320b416482e1 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -520,6 +520,11 @@ static void port_assign(struct execlist_port *port, struct i915_request *rq) if (port_isset(port)) i915_request_put(port_request(port)); + if (rq->sseu.value != rq->engine->last_sseu.value) { + rq->engine->last_sseu = rq->sseu; + atomic_inc(&rq->engine->sseu_transitions); + } + port_set(port, port_pack(i915_request_get(rq), port_count(port))); } @@ -779,6 +784,7 @@ execlists_cancel_port_requests(struct intel_engine_execlists * const execlists) while (num_ports-- && port_isset(port)) { struct i915_request *rq = port_request(port); + bool completed = i915_request_completed(rq); GEM_TRACE("%s:port%u global=%d (fence %llx:%d), (current %d)\n", rq->engine->name, @@ -789,10 +795,18 @@ execlists_cancel_port_requests(struct intel_engine_execlists * const execlists) GEM_BUG_ON(!execlists->active); execlists_context_schedule_out(rq, - i915_request_completed(rq) ? + completed ? INTEL_CONTEXT_SCHEDULE_OUT : INTEL_CONTEXT_SCHEDULE_PREEMPTED); + /* + * Update the last known sseu configuration to the first + * uncompleted request. Notice this works because we pop the + * requests out of the ports in reverse order. + */ + if (!completed) + rq->engine->last_sseu = rq->sseu; + i915_request_put(rq); memset(port, 0, sizeof(*port)); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 010750e8ee44..cc7e73730469 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -343,6 +343,18 @@ struct intel_engine_cs { struct drm_i915_gem_object *default_state; + /** + * @last_sseu: The last SSEU configuration submitted to the + * hardware. Set to 0 if unknown. + */ + union intel_sseu last_sseu; + + /** + * @sseu_transitions: A counter of the number of powergating + * transition this engine has gone through. + */ + atomic_t sseu_transitions; + atomic_t irq_count; unsigned long irq_posted; #define ENGINE_IRQ_BREADCRUMB 0