diff mbox

[053/262] drm/i915: Split control of rps and rc6

Message ID 20180517060738.19193-53-chris@chris-wilson.co.uk (mailing list archive)
State New, archived
Headers show

Commit Message

Chris Wilson May 17, 2018, 6:04 a.m. UTC 
Allow ourselves to individually toggle rps or rc6. This will be used
later when we want to enable rps/rc6 at different phases during the
device bring up.

Whilst here, convert the intel_$verb_gt_powersave over to
intel_gt_pm_$verb scheme.

v2: Resurrect llc_pstate, we will need to restore state on resume.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.c      |   7 +-
 drivers/gpu/drm/i915/i915_gem.c      |  23 +++---
 drivers/gpu/drm/i915/intel_display.c |   6 +-
 drivers/gpu/drm/i915/intel_gt_pm.c   | 109 +++++++++++++++++----------
 drivers/gpu/drm/i915/intel_gt_pm.h   |  18 +++--
 5 files changed, 102 insertions(+), 61 deletions(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5c6fe51eb45a..6914b08c69c0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -944,6 +944,7 @@  static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 	intel_wopcm_init_early(&dev_priv->wopcm);
 	intel_uc_init_early(dev_priv);
 	intel_pm_setup(dev_priv);
+	intel_gt_pm_init_early(dev_priv);
 	intel_init_dpio(dev_priv);
 	intel_power_domains_init(dev_priv);
 	intel_irq_init(dev_priv);
@@ -1073,7 +1074,7 @@  static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
  */
 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 {
-	intel_sanitize_gt_powersave(dev_priv);
+	intel_gt_pm_sanitize(dev_priv);
 	intel_uncore_fini(dev_priv);
 	i915_mmio_cleanup(dev_priv);
 	pci_dev_put(dev_priv->bridge_dev);
@@ -1182,7 +1183,7 @@  static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 	intel_uncore_sanitize(dev_priv);
 
 	/* BIOS often leaves RC6 enabled, but disable it for hw init */
-	intel_sanitize_gt_powersave(dev_priv);
+	intel_gt_pm_sanitize(dev_priv);
 
 	intel_opregion_setup(dev_priv);
 
@@ -1722,7 +1723,7 @@  static int i915_drm_resume(struct drm_device *dev)
 	int ret;
 
 	disable_rpm_wakeref_asserts(dev_priv);
-	intel_sanitize_gt_powersave(dev_priv);
+	intel_gt_pm_sanitize(dev_priv);
 
 	ret = i915_ggtt_enable_hw(dev_priv);
 	if (ret)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a19a94c8ac92..b056c6d63e18 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -202,7 +202,10 @@  void i915_gem_unpark(struct drm_i915_private *i915)
 	if (unlikely(++i915->gt.epoch == 0)) /* keep 0 as invalid */
 		i915->gt.epoch = 1;
 
-	intel_enable_gt_powersave(i915);
+	intel_gt_pm_enable_rps(i915);
+	intel_gt_pm_enable_rc6(i915);
+	intel_gt_pm_enable_llc(i915);
+
 	i915_update_gfx_val(i915);
 	if (INTEL_GEN(i915) >= 6)
 		gen6_rps_busy(i915);
@@ -5394,10 +5397,12 @@  int i915_gem_init(struct drm_i915_private *dev_priv)
 		goto err_unlock;
 	}
 
+	intel_gt_pm_init(dev_priv);
+
 	ret = i915_gem_contexts_init(dev_priv);
 	if (ret) {
 		GEM_BUG_ON(ret == -EIO);
-		goto err_ggtt;
+		goto err_pm;
 	}
 
 	ret = intel_engines_init(dev_priv);
@@ -5406,11 +5411,9 @@  int i915_gem_init(struct drm_i915_private *dev_priv)
 		goto err_context;
 	}
 
-	intel_init_gt_powersave(dev_priv);
-
 	ret = intel_uc_init(dev_priv);
 	if (ret)
-		goto err_pm;
+		goto err_engines;
 
 	ret = i915_gem_init_hw(dev_priv);
 	if (ret)
@@ -5458,15 +5461,15 @@  int i915_gem_init(struct drm_i915_private *dev_priv)
 	intel_uc_fini_hw(dev_priv);
 err_uc_init:
 	intel_uc_fini(dev_priv);
-err_pm:
-	if (ret != -EIO) {
-		intel_cleanup_gt_powersave(dev_priv);
+err_engines:
+	if (ret != -EIO)
 		i915_gem_cleanup_engines(dev_priv);
-	}
 err_context:
 	if (ret != -EIO)
 		i915_gem_contexts_fini(dev_priv);
-err_ggtt:
+err_pm:
+	if (ret != -EIO)
+		intel_gt_pm_fini(dev_priv);
 err_unlock:
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 	mutex_unlock(&dev_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 84ef96659b51..65688f7c9642 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15685,7 +15685,9 @@  void intel_modeset_cleanup(struct drm_device *dev)
 	flush_work(&dev_priv->atomic_helper.free_work);
 	WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
 
-	intel_disable_gt_powersave(dev_priv);
+	intel_gt_pm_disable_llc(dev_priv);
+	intel_gt_pm_disable_rc6(dev_priv);
+	intel_gt_pm_disable_rps(dev_priv);
 
 	/*
 	 * Interrupts and polling as the first thing to avoid creating havoc.
@@ -15714,7 +15716,7 @@  void intel_modeset_cleanup(struct drm_device *dev)
 
 	intel_cleanup_overlay(dev_priv);
 
-	intel_cleanup_gt_powersave(dev_priv);
+	intel_gt_pm_fini(dev_priv);
 
 	intel_teardown_gmbus(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c
index b69ddb5be3e4..35d7410fdf8f 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -2400,11 +2400,15 @@  static void intel_init_emon(struct drm_i915_private *dev_priv)
 	dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
 }
 
-void intel_sanitize_gt_powersave(struct drm_i915_private *i915)
+void intel_gt_pm_sanitize(struct drm_i915_private *i915)
 {
-	i915->gt_pm.rps.enabled = true; /* force RPS disabling */
+	intel_gt_pm_disable_llc(i915);
+
 	i915->gt_pm.rc6.enabled = true; /* force RC6 disabling */
-	intel_disable_gt_powersave(i915);
+	intel_gt_pm_disable_rc6(i915);
+
+	i915->gt_pm.rps.enabled = true; /* force RPS disabling */
+	intel_gt_pm_disable_rps(i915);
 
 	if (INTEL_GEN(i915) >= 11)
 		gen11_reset_rps_interrupts(i915);
@@ -2412,12 +2416,17 @@  void intel_sanitize_gt_powersave(struct drm_i915_private *i915)
 		gen6_reset_rps_interrupts(i915);
 }
 
-void intel_init_gt_powersave(struct drm_i915_private *i915)
+void intel_gt_pm_init_early(struct drm_i915_private *i915)
 {
 	struct intel_rps *rps = &i915->gt_pm.rps;
 
 	mutex_init(&rps->lock);
 	INIT_WORK(&rps->work, intel_rps_work);
+}
+
+void intel_gt_pm_init(struct drm_i915_private *i915)
+{
+	struct intel_rps *rps = &i915->gt_pm.rps;
 
 	if (HAS_GUC_SCHED(i915))
 		rps->guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
@@ -2494,19 +2503,7 @@  void intel_init_gt_powersave(struct drm_i915_private *i915)
 	mutex_unlock(&rps->lock);
 }
 
-static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
-{
-	lockdep_assert_held(&i915->gt_pm.rps.lock);
-
-	if (i915->gt_pm.llc_pstate.enabled)
-		return;
-
-	gen6_update_ring_freq(i915);
-
-	i915->gt_pm.llc_pstate.enabled = true;
-}
-
-static void intel_enable_rc6(struct drm_i915_private *i915)
+static void __enable_rc6(struct drm_i915_private *i915)
 {
 	lockdep_assert_held(&i915->gt_pm.rps.lock);
 
@@ -2527,7 +2524,17 @@  static void intel_enable_rc6(struct drm_i915_private *i915)
 	i915->gt_pm.rc6.enabled = true;
 }
 
-static void intel_enable_rps(struct drm_i915_private *i915)
+void intel_gt_pm_enable_rc6(struct drm_i915_private *i915)
+{
+	if (!HAS_RC6(i915))
+		return;
+
+	mutex_lock(&i915->gt_pm.rps.lock);
+	__enable_rc6(i915);
+	mutex_unlock(&i915->gt_pm.rps.lock);
+}
+
+static void __enable_rps(struct drm_i915_private *i915)
 {
 	struct intel_rps *rps = &i915->gt_pm.rps;
 
@@ -2560,37 +2567,38 @@  static void intel_enable_rps(struct drm_i915_private *i915)
 	rps->enabled = true;
 }
 
-void intel_enable_gt_powersave(struct drm_i915_private *i915)
+void intel_gt_pm_enable_rps(struct drm_i915_private *i915)
 {
-	/* Powersaving is controlled by the host when inside a VM */
-	if (intel_vgpu_active(i915))
+	if (!HAS_RPS(i915))
 		return;
 
 	mutex_lock(&i915->gt_pm.rps.lock);
-
-	if (HAS_RC6(i915))
-		intel_enable_rc6(i915);
-	if (HAS_RPS(i915))
-		intel_enable_rps(i915);
-	if (HAS_LLC(i915))
-		intel_enable_llc_pstate(i915);
-
+	__enable_rps(i915);
 	mutex_unlock(&i915->gt_pm.rps.lock);
 }
 
-static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
+static void __enable_llc(struct drm_i915_private *i915)
 {
 	lockdep_assert_held(&i915->gt_pm.rps.lock);
 
-	if (!i915->gt_pm.llc_pstate.enabled)
+	if (i915->gt_pm.llc_pstate.enabled)
 		return;
 
-	/* Currently there is no HW configuration to be done to disable. */
+	gen6_update_ring_freq(i915);
+	i915->gt_pm.llc_pstate.enabled = true;
+}
 
-	i915->gt_pm.llc_pstate.enabled = false;
+void intel_gt_pm_enable_llc(struct drm_i915_private *i915)
+{
+	if (!HAS_LLC(i915))
+		return;
+
+	mutex_lock(&i915->gt_pm.rps.lock);
+	__enable_llc(i915);
+	mutex_unlock(&i915->gt_pm.rps.lock);
 }
 
-static void intel_disable_rc6(struct drm_i915_private *i915)
+static void __disable_rc6(struct drm_i915_private *i915)
 {
 	lockdep_assert_held(&i915->gt_pm.rps.lock);
 
@@ -2609,7 +2617,14 @@  static void intel_disable_rc6(struct drm_i915_private *i915)
 	i915->gt_pm.rc6.enabled = false;
 }
 
-static void intel_disable_rps(struct drm_i915_private *i915)
+void intel_gt_pm_disable_rc6(struct drm_i915_private *i915)
+{
+	mutex_lock(&i915->gt_pm.rps.lock);
+	__disable_rc6(i915);
+	mutex_unlock(&i915->gt_pm.rps.lock);
+}
+
+static void __disable_rps(struct drm_i915_private *i915)
 {
 	lockdep_assert_held(&i915->gt_pm.rps.lock);
 
@@ -2630,19 +2645,31 @@  static void intel_disable_rps(struct drm_i915_private *i915)
 	i915->gt_pm.rps.enabled = false;
 }
 
-void intel_disable_gt_powersave(struct drm_i915_private *i915)
+void intel_gt_pm_disable_rps(struct drm_i915_private *i915)
 {
 	mutex_lock(&i915->gt_pm.rps.lock);
+	__disable_rps(i915);
+	mutex_unlock(&i915->gt_pm.rps.lock);
+}
+
+static void __disable_llc(struct drm_i915_private *i915)
+{
+	lockdep_assert_held(&i915->gt_pm.rps.lock);
 
-	intel_disable_rc6(i915);
-	intel_disable_rps(i915);
-	if (HAS_LLC(i915))
-		intel_disable_llc_pstate(i915);
+	if (!i915->gt_pm.llc_pstate.enabled)
+		return;
 
+	i915->gt_pm.llc_pstate.enabled = false;
+}
+
+void intel_gt_pm_disable_llc(struct drm_i915_private *i915)
+{
+	mutex_lock(&i915->gt_pm.rps.lock);
+	__disable_llc(i915);
 	mutex_unlock(&i915->gt_pm.rps.lock);
 }
 
-void intel_cleanup_gt_powersave(struct drm_i915_private *i915)
+void intel_gt_pm_fini(struct drm_i915_private *i915)
 {
 	if (IS_VALLEYVIEW(i915))
 		valleyview_cleanup_gt_powersave(i915);
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h b/drivers/gpu/drm/i915/intel_gt_pm.h
index bd400c9aed7c..0d95a52c1941 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/intel_gt_pm.h
@@ -93,12 +93,20 @@  struct intel_gt_pm {
 void intel_gpu_ips_init(struct drm_i915_private *i915);
 void intel_gpu_ips_teardown(void);
 
-void intel_sanitize_gt_powersave(struct drm_i915_private *i915);
+void intel_gt_pm_sanitize(struct drm_i915_private *i915);
 
-void intel_init_gt_powersave(struct drm_i915_private *i915);
-void intel_enable_gt_powersave(struct drm_i915_private *i915);
-void intel_disable_gt_powersave(struct drm_i915_private *i915);
-void intel_cleanup_gt_powersave(struct drm_i915_private *i915);
+void intel_gt_pm_init_early(struct drm_i915_private *i915);
+void intel_gt_pm_init(struct drm_i915_private *i915);
+void intel_gt_pm_fini(struct drm_i915_private *i915);
+
+void intel_gt_pm_enable_rps(struct drm_i915_private *i915);
+void intel_gt_pm_disable_rps(struct drm_i915_private *i915);
+
+void intel_gt_pm_enable_rc6(struct drm_i915_private *i915);
+void intel_gt_pm_disable_rc6(struct drm_i915_private *i915);
+
+void intel_gt_pm_enable_llc(struct drm_i915_private *i915);
+void intel_gt_pm_disable_llc(struct drm_i915_private *i915);
 
 void intel_gt_pm_irq_handler(struct drm_i915_private *i915, u32 pm_iir);