diff mbox

[5/5] drm/i915: Rename the remaining gen4 references to g4x in the DP code

Message ID 20180517170309.28630-5-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä May 17, 2018, 5:03 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

i965 does not have native DP. Let's rename the remaining gen4 references
in the DP code to g4x.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

Comments

Jani Nikula May 17, 2018, 5:49 p.m. UTC | #1 
On Thu, 17 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> i965 does not have native DP. Let's rename the remaining gen4 references
> in the DP code to g4x.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index cd4c60bfc4c2..102070940095 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -56,7 +56,7 @@ struct dp_link_dpll {
>  	struct dpll dpll;
>  };
>  
> -static const struct dp_link_dpll gen4_dpll[] = {
> +static const struct dp_link_dpll g4x_dpll[] = {
>  	{ 162000,
>  		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
>  	{ 270000,
> @@ -1550,8 +1550,8 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>  	int i, count = 0;
>  
>  	if (IS_G4X(dev_priv)) {
> -		divisor = gen4_dpll;
> -		count = ARRAY_SIZE(gen4_dpll);
> +		divisor = g4x_dpll;
> +		count = ARRAY_SIZE(g4x_dpll);
>  	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		divisor = pch_dpll;
>  		count = ARRAY_SIZE(pch_dpll);
> @@ -3451,7 +3451,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
>  }
>  
>  static uint32_t
> -gen4_signal_levels(uint8_t train_set)
> +g4x_signal_levels(uint8_t train_set)
>  {
>  	uint32_t	signal_levels = 0;
>  
> @@ -3572,7 +3572,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>  		signal_levels = snb_cpu_edp_signal_levels(train_set);
>  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
>  	} else {
> -		signal_levels = gen4_signal_levels(train_set);
> +		signal_levels = g4x_signal_levels(train_set);
>  		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
>  	}
Ville Syrjälä May 18, 2018, 2:27 p.m. UTC | #2 
On Thu, May 17, 2018 at 08:49:27PM +0300, Jani Nikula wrote:
> On Thu, 17 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > i965 does not have native DP. Let's rename the remaining gen4 references
> > in the DP code to g4x.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Thanks. Entire series pushed to dinq.

> 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
> >  1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index cd4c60bfc4c2..102070940095 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -56,7 +56,7 @@ struct dp_link_dpll {
> >  	struct dpll dpll;
> >  };
> >  
> > -static const struct dp_link_dpll gen4_dpll[] = {
> > +static const struct dp_link_dpll g4x_dpll[] = {
> >  	{ 162000,
> >  		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
> >  	{ 270000,
> > @@ -1550,8 +1550,8 @@ intel_dp_set_clock(struct intel_encoder *encoder,
> >  	int i, count = 0;
> >  
> >  	if (IS_G4X(dev_priv)) {
> > -		divisor = gen4_dpll;
> > -		count = ARRAY_SIZE(gen4_dpll);
> > +		divisor = g4x_dpll;
> > +		count = ARRAY_SIZE(g4x_dpll);
> >  	} else if (HAS_PCH_SPLIT(dev_priv)) {
> >  		divisor = pch_dpll;
> >  		count = ARRAY_SIZE(pch_dpll);
> > @@ -3451,7 +3451,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
> >  }
> >  
> >  static uint32_t
> > -gen4_signal_levels(uint8_t train_set)
> > +g4x_signal_levels(uint8_t train_set)
> >  {
> >  	uint32_t	signal_levels = 0;
> >  
> > @@ -3572,7 +3572,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> >  		signal_levels = snb_cpu_edp_signal_levels(train_set);
> >  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
> >  	} else {
> > -		signal_levels = gen4_signal_levels(train_set);
> > +		signal_levels = g4x_signal_levels(train_set);
> >  		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
> >  	}
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cd4c60bfc4c2..102070940095 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -56,7 +56,7 @@  struct dp_link_dpll {
 	struct dpll dpll;
 };
 
-static const struct dp_link_dpll gen4_dpll[] = {
+static const struct dp_link_dpll g4x_dpll[] = {
 	{ 162000,
 		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
 	{ 270000,
@@ -1550,8 +1550,8 @@  intel_dp_set_clock(struct intel_encoder *encoder,
 	int i, count = 0;
 
 	if (IS_G4X(dev_priv)) {
-		divisor = gen4_dpll;
-		count = ARRAY_SIZE(gen4_dpll);
+		divisor = g4x_dpll;
+		count = ARRAY_SIZE(g4x_dpll);
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		divisor = pch_dpll;
 		count = ARRAY_SIZE(pch_dpll);
@@ -3451,7 +3451,7 @@  static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
 }
 
 static uint32_t
-gen4_signal_levels(uint8_t train_set)
+g4x_signal_levels(uint8_t train_set)
 {
 	uint32_t	signal_levels = 0;
 
@@ -3572,7 +3572,7 @@  intel_dp_set_signal_levels(struct intel_dp *intel_dp)
 		signal_levels = snb_cpu_edp_signal_levels(train_set);
 		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
 	} else {
-		signal_levels = gen4_signal_levels(train_set);
+		signal_levels = g4x_signal_levels(train_set);
 		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
 	}