From patchwork Mon May 21 11:20:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lionel Landwerlin X-Patchwork-Id: 10414897 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1152C6032B for ; Mon, 21 May 2018 11:53:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 01DAE28755 for ; Mon, 21 May 2018 11:53:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EAD4928830; Mon, 21 May 2018 11:53:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A18EA28755 for ; Mon, 21 May 2018 11:53:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 077586F075; Mon, 21 May 2018 11:52:23 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4E4E96E001 for ; Mon, 21 May 2018 11:20:13 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 May 2018 04:20:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,426,1520924400"; d="scan'208";a="42615328" Received: from delly.ld.intel.com ([10.103.238.202]) by orsmga007.jf.intel.com with ESMTP; 21 May 2018 04:20:09 -0700 From: Lionel Landwerlin To: intel-gfx@lists.freedesktop.org Date: Mon, 21 May 2018 12:20:07 +0100 Message-Id: <20180521112007.16237-1-lionel.g.landwerlin@intel.com> X-Mailer: git-send-email 2.17.0 Subject: [Intel-gfx] [PATCH v3] drm/i915/cmdparser: Whitelist INSTPM instruction parsing disable bits X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP On Gen8+ this register is not priviledged and we want to use it in Mesa to implement a feature required by GPA called Null Hardware. The idea is to have the command parser turn 3DPRIMITIVE/GPGPU_WALKER into NOOPs. This patch just whitelists the bits that we need and that are currently not used by the kernel. v2: Bump the command parser revision (Chris) v3: Whitelist TEXTURE_PALETTE_LOAD_INSTRUCTION_DISABLE (Chris) Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_cmd_parser.c | 13 ++++++++++++- drivers/gpu/drm/i915/i915_reg.h | 5 +++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index 95478db9998b..ecf2aede04ed 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -534,6 +534,16 @@ struct drm_i915_reg_descriptor { { .addr = _reg ## _UDW(idx) } static const struct drm_i915_reg_descriptor gen7_render_regs[] = { + REG32(INSTPM, + .mask = ~((INSTPM_TEXTURE_PALETTE_LOAD_INSTRUCTION_DISABLE | + INSTPM_3D_STATE_INSTRUCTION_DISABLE | + INSTPM_3D_RENDERING_INSTRUCTION_DISABLE | + INSTPM_MEDIA_INSTRUCTION_DISABLE) << 16 | + (INSTPM_TEXTURE_PALETTE_LOAD_INSTRUCTION_DISABLE | + INSTPM_3D_STATE_INSTRUCTION_DISABLE | + INSTPM_3D_RENDERING_INSTRUCTION_DISABLE | + INSTPM_MEDIA_INSTRUCTION_DISABLE)), + .value = 0), REG64(GPGPU_THREADS_DISPATCHED), REG64(HS_INVOCATION_COUNT), REG64(DS_INVOCATION_COUNT), @@ -1382,6 +1392,7 @@ int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv) * the parser enabled. * 9. Don't whitelist or handle oacontrol specially, as ownership * for oacontrol state is moving to i915-perf. + * 10. Whitelist bits of INSTPM on Ivybridge & Haswell. */ - return 9; + return 10; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 196a0eb79272..ebfc9cdc5378 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2530,7 +2530,12 @@ enum i915_power_well_id { be delivered when out of C3. */ #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ #define INSTPM_TLB_INVALIDATE (1<<9) +#define INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 6) /* GEN6+ */ #define INSTPM_SYNC_FLUSH (1<<5) +#define INSTPM_MEDIA_INSTRUCTION_DISABLE (1 << 3) /* GEN6+ */ +#define INSTPM_3D_RENDERING_INSTRUCTION_DISABLE (1 << 2) /* GEN6+ */ +#define INSTPM_3D_STATE_INSTRUCTION_DISABLE (1 << 1) /* GEN6+ */ +#define INSTPM_TEXTURE_PALETTE_LOAD_INSTRUCTION_DISABLE (1 << 0) /* GEN6+ */ #define ACTHD _MMIO(0x20c8) #define MEM_MODE _MMIO(0x20cc) #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */