| Message ID | 20180522002558.29262-23-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
>-----Original Message----- >From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of >Paulo Zanoni >Sent: Monday, May 21, 2018 5:26 PM >To: intel-gfx@lists.freedesktop.org >Cc: Zanoni, Paulo R <paulo.r.zanoni@intel.com> >Subject: [Intel-gfx] [PATCH 22/24] drm/i915/icl: Update FIA supported lane count >for hpd. > >From: Animesh Manna <animesh.manna@intel.com> > >In ICL, Flexible IO Adapter (FIA) muxes data and clocks of USB 3.1, tbt and display >controller. In DP alt mode FIA configure the number of lanes and will be used >apart from DPCD read to calculate max available lanes for DP enablement. > >Signed-off-by: Animesh Manna <animesh.manna@intel.com> >[Paulo: significant rewrite of the patch.] >Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Looks good. Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >--- > drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_dp.c | >33 ++++++++++++++++++++++++++++++++- > 2 files changed, 37 insertions(+), 1 deletion(-) > >diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >index 42cbace4c61e..2a501e7590bf 100644 >--- a/drivers/gpu/drm/i915/i915_reg.h >+++ b/drivers/gpu/drm/i915/i915_reg.h >@@ -10033,4 +10033,9 @@ enum skl_power_gate { > #define PORT_TX_DFLEXDPCSSS _MMIO(0x163894) > #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port)) > >+#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0) >+#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8) >+#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8)) >+#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8)) >+ > #endif /* _I915_REG_H_ */ >diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >index f25f871e7c22..a883a3264e56 100644 >--- a/drivers/gpu/drm/i915/intel_dp.c >+++ b/drivers/gpu/drm/i915/intel_dp.c >@@ -176,14 +176,45 @@ static int intel_dp_max_common_rate(struct intel_dp >*intel_dp) > return intel_dp->common_rates[intel_dp->num_common_rates - 1]; } > >+static int intel_dp_get_fia_supported_lane_count(struct intel_dp >+*intel_dp) { >+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); >+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); >+ enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); >+ u32 lane_info; >+ >+ if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC) >+ return 4; >+ >+ lane_info = (I915_READ(PORT_TX_DFLEXDPSP) & >+ DP_LANE_ASSIGNMENT_MASK(tc_port)) >> >+ DP_LANE_ASSIGNMENT_SHIFT(tc_port); >+ >+ switch (lane_info) { >+ default: >+ MISSING_CASE(lane_info); >+ case 1: >+ case 2: >+ case 4: >+ case 8: >+ return 1; >+ case 3: >+ case 12: >+ return 2; >+ case 15: >+ return 4; >+ } >+} >+ > /* Theoretical max between source and sink */ static int >intel_dp_max_common_lane_count(struct intel_dp *intel_dp) { > struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > int source_max = intel_dig_port->max_lanes; > int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); >+ int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp); > >- return min(source_max, sink_max); >+ return min3(source_max, sink_max, fia_max); > } > > int intel_dp_max_lane_count(struct intel_dp *intel_dp) >-- >2.14.3 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx@lists.freedesktop.org >https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 42cbace4c61e..2a501e7590bf 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10033,4 +10033,9 @@ enum skl_power_gate { #define PORT_TX_DFLEXDPCSSS _MMIO(0x163894) #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port)) +#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0) +#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8) +#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8)) +#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8)) + #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index f25f871e7c22..a883a3264e56 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -176,14 +176,45 @@ static int intel_dp_max_common_rate(struct intel_dp *intel_dp) return intel_dp->common_rates[intel_dp->num_common_rates - 1]; } +static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp) +{ + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); + u32 lane_info; + + if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC) + return 4; + + lane_info = (I915_READ(PORT_TX_DFLEXDPSP) & + DP_LANE_ASSIGNMENT_MASK(tc_port)) >> + DP_LANE_ASSIGNMENT_SHIFT(tc_port); + + switch (lane_info) { + default: + MISSING_CASE(lane_info); + case 1: + case 2: + case 4: + case 8: + return 1; + case 3: + case 12: + return 2; + case 15: + return 4; + } +} + /* Theoretical max between source and sink */ static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); int source_max = intel_dig_port->max_lanes; int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); + int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp); - return min(source_max, sink_max); + return min3(source_max, sink_max, fia_max); } int intel_dp_max_lane_count(struct intel_dp *intel_dp)