| Message ID | 20180522002558.29262-9-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, May 21, 2018 at 05:25:42PM -0700, Paulo Zanoni wrote: > From: "Sripada, Radhakrishna" <radhakrishna.sripada@intel.com> > > On ICL we need to map VBT DDC Pin to BSpec DDC Pin. > Adding ICL Pin Values. > > According to VBT > Block 2 (General Bytes Definition) > DDC Bus > > +----------+-----------+--------------------+ > | DDI Type | VBT Value | BSpec Mapped Value | > +----------+-----------+--------------------+ > | DDI-A | 0x1 | 0x1 | > | DDI-B | 0x2 | 0x2 | > | PORT-1 | 0x4 | 0x9 | > | PORT-2 | 0x5 | 0xA | > | PORT-3 | 0x6 | 0xB | > | PORT-4 | 0x7 | 0xC | > +----------+-----------+--------------------+ > > Cc: James Ausmus <james.ausmus@intel.com> > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > Cc: Clinton Taylor <clinton.a.taylor@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > [Paulo: checkpatch fixes.] > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Matches BSpec, looks good! Reviewed-by: James Ausmus <james.ausmus@intel.com> > --- > drivers/gpu/drm/i915/intel_bios.c | 35 +++++++++++++++++++++++++++-------- > drivers/gpu/drm/i915/intel_vbt_defs.h | 6 ++++++ > 2 files changed, 33 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c > index 54270bdde100..34e9bca36c14 100644 > --- a/drivers/gpu/drm/i915/intel_bios.c > +++ b/drivers/gpu/drm/i915/intel_bios.c > @@ -1197,18 +1197,37 @@ static const u8 cnp_ddc_pin_map[] = { > [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */ > }; > > +static const u8 icp_ddc_pin_map[] = { > + [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, > + [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, > + [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP, > + [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP, > + [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP, > + [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP, > +}; > + > static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) > { > - if (HAS_PCH_CNP(dev_priv)) { > - if (vbt_pin < ARRAY_SIZE(cnp_ddc_pin_map)) { > - return cnp_ddc_pin_map[vbt_pin]; > - } else { > - DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", vbt_pin); > - return 0; > - } > + const u8 *ddc_pin_map; > + int n_entries; > + > + if (HAS_PCH_ICP(dev_priv)) { > + ddc_pin_map = icp_ddc_pin_map; > + n_entries = ARRAY_SIZE(icp_ddc_pin_map); > + } else if (HAS_PCH_CNP(dev_priv)) { > + ddc_pin_map = cnp_ddc_pin_map; > + n_entries = ARRAY_SIZE(cnp_ddc_pin_map); > + } else { > + /* Assuming direct map */ > + return vbt_pin; > } > > - return vbt_pin; > + if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0) > + return ddc_pin_map[vbt_pin]; > + > + DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", > + vbt_pin); > + return 0; > } > > static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, > diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h > index 458468237b5f..7c798c18600e 100644 > --- a/drivers/gpu/drm/i915/intel_vbt_defs.h > +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h > @@ -318,6 +318,12 @@ enum vbt_gmbus_ddi { > DDC_BUS_DDI_C, > DDC_BUS_DDI_D, > DDC_BUS_DDI_F, > + ICL_DDC_BUS_DDI_A = 0x1, > + ICL_DDC_BUS_DDI_B, > + ICL_DDC_BUS_PORT_1 = 0x4, > + ICL_DDC_BUS_PORT_2, > + ICL_DDC_BUS_PORT_3, > + ICL_DDC_BUS_PORT_4, > }; > > #define VBT_DP_MAX_LINK_RATE_HBR3 0 > -- > 2.14.3 >
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 54270bdde100..34e9bca36c14 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -1197,18 +1197,37 @@ static const u8 cnp_ddc_pin_map[] = { [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */ }; +static const u8 icp_ddc_pin_map[] = { + [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, + [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, + [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP, + [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP, + [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP, + [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP, +}; + static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) { - if (HAS_PCH_CNP(dev_priv)) { - if (vbt_pin < ARRAY_SIZE(cnp_ddc_pin_map)) { - return cnp_ddc_pin_map[vbt_pin]; - } else { - DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", vbt_pin); - return 0; - } + const u8 *ddc_pin_map; + int n_entries; + + if (HAS_PCH_ICP(dev_priv)) { + ddc_pin_map = icp_ddc_pin_map; + n_entries = ARRAY_SIZE(icp_ddc_pin_map); + } else if (HAS_PCH_CNP(dev_priv)) { + ddc_pin_map = cnp_ddc_pin_map; + n_entries = ARRAY_SIZE(cnp_ddc_pin_map); + } else { + /* Assuming direct map */ + return vbt_pin; } - return vbt_pin; + if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0) + return ddc_pin_map[vbt_pin]; + + DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", + vbt_pin); + return 0; } static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h index 458468237b5f..7c798c18600e 100644 --- a/drivers/gpu/drm/i915/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h @@ -318,6 +318,12 @@ enum vbt_gmbus_ddi { DDC_BUS_DDI_C, DDC_BUS_DDI_D, DDC_BUS_DDI_F, + ICL_DDC_BUS_DDI_A = 0x1, + ICL_DDC_BUS_DDI_B, + ICL_DDC_BUS_PORT_1 = 0x4, + ICL_DDC_BUS_PORT_2, + ICL_DDC_BUS_PORT_3, + ICL_DDC_BUS_PORT_4, }; #define VBT_DP_MAX_LINK_RATE_HBR3 0