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[192.55.54.38]) by smtp.gmail.com with ESMTPSA id v16-v6sm83862345pfj.123.2018.05.24.17.36.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 24 May 2018 17:36:40 -0700 (PDT) Date: Thu, 24 May 2018 17:36:37 -0700 From: Lucas De Marchi To: Paulo Zanoni Message-ID: <20180525003635.GB2951@ldmartin-desk.amr.corp.intel.com> References: <20180522002558.29262-1-paulo.r.zanoni@intel.com> <20180524234241.3665-1-paulo.r.zanoni@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20180524234241.3665-1-paulo.r.zanoni@intel.com> User-Agent: Mutt/1.9.5 (2018-04-13) Subject: Re: [Intel-gfx] [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP On Thu, May 24, 2018 at 04:42:36PM -0700, Paulo Zanoni wrote: > From: Mahesh Kumar > > ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12 > mapped to tc ports[1-4]. > This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO > pin mapping table. > > Cc: Anusha Srivatsa > Cc: Madhav Chauhan > Cc: Lucas De Marchi > Signed-off-by: Mahesh Kumar > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > drivers/gpu/drm/i915/intel_i2c.c | 12 ++++++------ > 3 files changed, 11 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 452356a4af07..e48b717769b2 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3015,6 +3015,10 @@ enum i915_power_well_id { > #define GPIOF _MMIO(0x5024) > #define GPIOG _MMIO(0x5028) > #define GPIOH _MMIO(0x502c) > +#define GPIOJ _MMIO(0x5034) > +#define GPIOK _MMIO(0x5038) > +#define GPIOL _MMIO(0x503C) > +#define GPIOM _MMIO(0x5040) I was reviewing again this and I think again I was puzzled why the spec has them as 0xc5034, ... Probably same conclusion as I had when I first reviewed this. Maybe it would be nice to add a comment to PCH_GPIO* saying PCH_GPIOA is used only for calculation the gpio base and remove the rest. I can send this is a separate patch, what do you think? -------8<------- -------8<------- Other than that, Reviewed-by: Lucas De Marchi > # define GPIO_CLOCK_DIR_MASK (1 << 0) > # define GPIO_CLOCK_DIR_IN (0 << 1) > # define GPIO_CLOCK_DIR_OUT (1 << 1) > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > index 75f02a0e7d39..3db2459c79b1 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -2276,7 +2276,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, > ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); > else if (HAS_PCH_CNP(dev_priv)) > ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); > - else if (IS_ICELAKE(dev_priv)) > + else if (HAS_PCH_ICP(dev_priv)) > ddc_pin = icl_port_to_ddc_pin(dev_priv, port); > else > ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c > index e6875509bcd9..b91e418028cb 100644 > --- a/drivers/gpu/drm/i915/intel_i2c.c > +++ b/drivers/gpu/drm/i915/intel_i2c.c > @@ -77,12 +77,12 @@ static const struct gmbus_pin gmbus_pins_cnp[] = { > }; > > static const struct gmbus_pin gmbus_pins_icp[] = { > - [GMBUS_PIN_1_BXT] = { "dpa", GPIOA }, > - [GMBUS_PIN_2_BXT] = { "dpb", GPIOB }, > - [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOC }, > - [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOD }, > - [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOE }, > - [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOF }, > + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, > + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, > + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, > + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, > + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, > + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, > }; > > /* pin is expected to be valid */ > -- > 2.14.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6953419881c4..40b9aa57078b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7442,12 +7442,8 @@ enum { #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) +/* Used just for calculating the gpio base for PCH */ #define PCH_GPIOA _MMIO(0xc5010) -#define PCH_GPIOB _MMIO(0xc5014) -#define PCH_GPIOC _MMIO(0xc5018) -#define PCH_GPIOD _MMIO(0xc501c) -#define PCH_GPIOE _MMIO(0xc5020) -#define PCH_GPIOF _MMIO(0xc5024) #define PCH_GMBUS0 _MMIO(0xc5100) #define PCH_GMBUS1 _MMIO(0xc5104)