From patchwork Tue May 29 11:16:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 10435011 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D396D602CC for ; Tue, 29 May 2018 11:16:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C32E928305 for ; Tue, 29 May 2018 11:16:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B7D0C286E6; Tue, 29 May 2018 11:16:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1D5CD28305 for ; Tue, 29 May 2018 11:16:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A625894C1; Tue, 29 May 2018 11:16:23 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6DEC16E3AB; Tue, 29 May 2018 11:16:20 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 11874962-1500050 for multiple; Tue, 29 May 2018 12:16:04 +0100 Received: by haswell.alporthouse.com (sSMTP sendmail emulation); Tue, 29 May 2018 12:16:06 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Tue, 29 May 2018 12:16:05 +0100 Message-Id: <20180529111605.18246-1-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.17.0 X-Originating-IP: 78.156.65.138 X-Country: code=GB country="United Kingdom" ip=78.156.65.138 Subject: [Intel-gfx] [PATCH i-g-t] igt/gem_ctx_isolation: Test INSTPM back to gen6 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Lionel pointed out that INSTPM was context saved, at least from gen6, not from gen9. The only caveat is that INSTPM is a masked register (the upper 16bits are a write-enable mask, the lower 16bits the value to change) and also contains a read-only counter bit (which counts flushes, and so flip flops between batches). Being a non-privileged register that userspace wants to manipulate, it is writable and readable from a userspace batch, so we can test whether or not a write from one context is visible from a second. Signed-off-by: Chris Wilson Cc: Lionel Landwerlin Cc: Joonas Lahtinen Reviewed-by: Lionel Landwerlin --- tests/gem_ctx_isolation.c | 51 ++++++++++++++++++++++++++++++++------- 1 file changed, 42 insertions(+), 9 deletions(-) diff --git a/tests/gem_ctx_isolation.c b/tests/gem_ctx_isolation.c index 4968e3678..fe7d3490c 100644 --- a/tests/gem_ctx_isolation.c +++ b/tests/gem_ctx_isolation.c @@ -63,10 +63,12 @@ static const struct named_register { unsigned int engine_mask; uint32_t offset; uint32_t count; + uint32_t ignore_bits; + bool masked; } nonpriv_registers[] = { { "NOPID", NOCTX, RCS0, 0x2094 }, { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc }, - { "INSTPM", GEN9, RCS0, 0x20c0 }, + { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true }, { "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 }, { "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 }, { "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 }, @@ -167,6 +169,17 @@ static const char *register_name(uint32_t offset, char *buf, size_t len) return "unknown"; } +static const struct named_register *lookup_register(uint32_t offset) +{ + for (const struct named_register *r = nonpriv_registers; r->name; r++) { + unsigned int width = r->count ? 4*r->count : 4; + if (offset >= r->offset && offset < r->offset + width) + return r; + } + + return NULL; +} + static bool ignore_register(uint32_t offset) { for (const struct named_register *r = ignore_registers; r->name; r++) { @@ -283,7 +296,10 @@ static void write_regs(int fd, count--; offset += 4) { *b++ = 0x22 << 23 | 1; /* LRI */ *b++ = offset; - *b++ = value; + if (r->masked) + *b++ = value | 0xffffu << 16; + else + *b++ = value; } } *b++ = MI_BATCH_BUFFER_END; @@ -424,14 +440,31 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who) num_errors = 0; for (unsigned int n = 0; n < NUM_REGS; n++) { + const struct named_register *r; uint32_t offset = n * sizeof(uint32_t); - if (a[n] != b[n] && !ignore_register(offset)) { - igt_warn("Register 0x%04x (%s): A=%08x B=%08x\n", - offset, - register_name(offset, buf, sizeof(buf)), - a[n], b[n]); - num_errors++; - } + uint32_t mask; + + if (a[n] == b[n]) + continue; + + if (ignore_register(offset)) + continue; + + mask = ~0u; + r = lookup_register(offset); + if (r && r->masked) + mask >>= 16; + if (r && r->ignore_bits) + mask &= ~r->ignore_bits; + + if ((a[n] & mask) == (b[n] & mask)) + continue; + + igt_warn("Register 0x%04x (%s): A=%08x B=%08x\n", + offset, + register_name(offset, buf, sizeof(buf)), + a[n] & mask, b[n] & mask); + num_errors++; } munmap(b, regs_size); munmap(a, regs_size);