From patchwork Tue May 29 18:28:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 10436719 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id ED653601E9 for ; Tue, 29 May 2018 18:28:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DAD492855A for ; Tue, 29 May 2018 18:28:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CB5FB285FF; Tue, 29 May 2018 18:28:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 667E22855A for ; Tue, 29 May 2018 18:28:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2614D6E4C0; Tue, 29 May 2018 18:28:14 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id C1F9F6E4A8 for ; Tue, 29 May 2018 18:28:12 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 May 2018 11:28:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,457,1520924400"; d="scan'208";a="51561570" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga002.fm.intel.com with SMTP; 29 May 2018 11:28:08 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 29 May 2018 21:28:07 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 29 May 2018 21:28:01 +0300 Message-Id: <20180529182804.8571-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180529182804.8571-1-ville.syrjala@linux.intel.com> References: <20180529182804.8571-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Fix VLV/CHV sprite src colorkey mask X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä VLV/CHV sprites use the old plane C layout of the colorkey mask register. Insted of 8 bit masks for each RGB component in the lower bits, the register only has the per channel src key enable bits. On g4x+ sprites those bits are 24,25,26 whereas on the old plane C and VLV/CHV sprites they are bits 0,1,2. Since userspace assumes the g4x+ layout let's just shift enable bits down and ignore the full masks. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_sprite.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 6164c2ca20c3..f6be9b1b9c3a 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -548,7 +548,7 @@ vlv_update_plane(struct intel_plane *plane, if (key->flags) { I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value); I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value); - I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask); + I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask >> 24); } I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]); I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);