From patchwork Wed May 30 13:53:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Piotr_Pi=C3=B3rkowski?= X-Patchwork-Id: 10439267 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 726C660327 for ; Wed, 30 May 2018 15:19:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 612CA29045 for ; Wed, 30 May 2018 15:19:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 55E7D29049; Wed, 30 May 2018 15:19:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 08BD529045 for ; Wed, 30 May 2018 15:19:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 55E0C6E947; Wed, 30 May 2018 13:55:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 974346E947 for ; Wed, 30 May 2018 13:55:31 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 May 2018 06:55:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,460,1520924400"; d="scan'208";a="228525676" Received: from irsmsx105.ger.corp.intel.com ([163.33.3.28]) by orsmga005.jf.intel.com with ESMTP; 30 May 2018 06:55:29 -0700 Received: from localhost (172.28.172.32) by irsmsx105.ger.corp.intel.com (163.33.3.28) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 30 May 2018 14:55:29 +0100 From: Piotr Piorkowski To: Date: Wed, 30 May 2018 15:53:34 +0200 Message-ID: <20180530135334.25113-7-piotr.piorkowski@intel.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180530135334.25113-1-piotr.piorkowski@intel.com> References: <20180530135334.25113-1-piotr.piorkowski@intel.com> MIME-Version: 1.0 X-Originating-IP: [172.28.172.32] Subject: [Intel-gfx] [PATCH 7/7] drm/i915/guc: Add support for define guc_log_size in megabytes. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP At this moment we can define GuC logs sizes only using pages. But GuC also allows use for this values expressed in megabytes. Lets add support for define guc_log_size in megabytes when we debug of GuC. Signed-off-by: Piotr Piórkowski Cc: Michal Wajdeczko Cc: Michał Winiarski Cc: Joonas Lahtinen Cc: Chris Wilson --- drivers/gpu/drm/i915/intel_guc.c | 12 ++++++++++-- drivers/gpu/drm/i915/intel_guc_log.h | 6 ++++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index e15047fedb45..5a42db47521b 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -263,7 +263,13 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc) u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT; u32 flags; + #if (((CRASH_BUFFER_SIZE) % (1 << 20)) == 0) + #define UNIT (1 << 20) + #define FLAG GUC_LOG_ALLOC_IN_MEGABYTE + #else #define UNIT (4 << 10) + #define FLAG 0 + #endif BUILD_BUG_ON(!CRASH_BUFFER_SIZE); BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, UNIT)); @@ -280,13 +286,15 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc) (GUC_LOG_ISR_MASK >> GUC_LOG_ISR_SHIFT)); flags = GUC_LOG_VALID | - GUC_LOG_NOTIFY_ON_HALF_FULL | - ((CRASH_BUFFER_SIZE/UNIT - 1) << GUC_LOG_CRASH_SHIFT) | + GUC_LOG_NOTIFY_ON_HALF_FULL; + flags |= FLAG; + flags |= ((CRASH_BUFFER_SIZE/UNIT - 1) << GUC_LOG_CRASH_SHIFT) | ((DPC_BUFFER_SIZE/UNIT - 1) << GUC_LOG_DPC_SHIFT) | ((ISR_BUFFER_SIZE/UNIT - 1) << GUC_LOG_ISR_SHIFT) | (offset << GUC_LOG_BUF_ADDR_SHIFT); #undef UNIT + #undef FLAG return flags; } diff --git a/drivers/gpu/drm/i915/intel_guc_log.h b/drivers/gpu/drm/i915/intel_guc_log.h index 1b3afdae6d0d..de39b965ae7a 100644 --- a/drivers/gpu/drm/i915/intel_guc_log.h +++ b/drivers/gpu/drm/i915/intel_guc_log.h @@ -34,9 +34,15 @@ struct intel_guc; +#ifdef DRM_I915_DEBUG_GUC +#define CRASH_BUFFER_SIZE 2097152 +#define DPC_BUFFER_SIZE 8388608 +#define ISR_BUFFER_SIZE 8388608 +#else #define CRASH_BUFFER_SIZE 8192 #define DPC_BUFFER_SIZE 32768 #define ISR_BUFFER_SIZE 32768 +#endif /* * While we're using plain log level in i915, GuC controls are much more...