From patchwork Wed May 30 14:33:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lionel Landwerlin X-Patchwork-Id: 10439363 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C1BD3602CC for ; Wed, 30 May 2018 16:18:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ACE7A27B2F for ; Wed, 30 May 2018 16:18:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A196F285FB; Wed, 30 May 2018 16:18:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2B37527B2F for ; Wed, 30 May 2018 16:18:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9DD0B6EBC4; Wed, 30 May 2018 14:34:04 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1DE7B6EBC4 for ; Wed, 30 May 2018 14:34:03 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 May 2018 07:34:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,460,1520924400"; d="scan'208";a="233172160" Received: from delly.ld.intel.com ([10.103.238.202]) by fmsmga006.fm.intel.com with ESMTP; 30 May 2018 07:34:02 -0700 From: Lionel Landwerlin To: intel-gfx@lists.freedesktop.org Date: Wed, 30 May 2018 15:33:53 +0100 Message-Id: <20180530143355.6611-6-lionel.g.landwerlin@intel.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530143355.6611-1-lionel.g.landwerlin@intel.com> References: <20180530143355.6611-1-lionel.g.landwerlin@intel.com> Subject: [Intel-gfx] [PATCH v9 5/7] drm/i915/perf: lock powergating configuration to default when active X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP If some of the contexts submitting workloads to the GPU have been configured to shutdown slices/subslices, we might loose the NOA configurations written in the NOA muxes. One possible solution to this problem is to reprogram the NOA muxes when we switch to a new context. We initially tried this in the workaround batchbuffer but some concerns where raised about the cost of reprogramming at every context switch. This solution is also not without consequences from the userspace point of view. Reprogramming of the muxes can only happen once the powergating configuration has changed (which happens after context switch). This means for a window of time during the recording, counters recorded by the OA unit might be invalid. This requires userspace dealing with OA reports to discard the invalid values. Minimizing the reprogramming could be implemented by tracking of the last programmed configuration somewhere in GGTT and use MI_PREDICATE to discard some of the programming commands, but the command streamer would still have to parse all the MI_LRI instructions in the workaround batchbuffer. Another solution, which this change implements, is to simply disregard the user requested configuration for the period of time when i915/perf is active. There is no known issue with this apart from a performance penality for some media workloads that benefit from running on a partially powergated GPU. We already prevent RC6 from affecting the programming so it doesn't sound completely unreasonable to hold on powergating for the same reason. v2: Leave RPCS programming in intel_lrc.c (Lionel) v3: Update for s/union intel_sseu/struct intel_sseu/ (Lionel) More to_intel_context() (Tvrtko) s/dev_priv/i915/ (Tvrtko) Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_drv.h | 15 +++++++++++++++ drivers/gpu/drm/i915/i915_perf.c | 23 ++++++++++++++++++----- drivers/gpu/drm/i915/intel_lrc.c | 11 +++++++---- drivers/gpu/drm/i915/intel_lrc.h | 3 +++ 4 files changed, 43 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 62ababfd39aa..25ffadfcd04b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3839,4 +3839,19 @@ static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) return I915_HWS_CSB_WRITE_INDEX; } +static inline struct intel_sseu +intel_engine_prepare_sseu(struct intel_engine_cs *engine, + struct intel_sseu sseu) +{ + struct drm_i915_private *i915 = engine->i915; + + /* + * If i915/perf is active, we want a stable powergating configuration + * on the system. The most natural configuration to take in that case + * is the default (i.e maximum the hardware can do). + */ + return i915->perf.oa.exclusive_stream ? + intel_device_default_sseu(i915) : sseu; +} + #endif diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index a5d98bda5c2e..4a62024cbf85 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1574,7 +1574,8 @@ static void hsw_disable_metric_set(struct drm_i915_private *dev_priv) */ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, u32 *reg_state, - const struct i915_oa_config *oa_config) + const struct i915_oa_config *oa_config, + struct intel_sseu sseu) { struct drm_i915_private *dev_priv = ctx->i915; u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset; @@ -1620,6 +1621,9 @@ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, CTX_REG(reg_state, state_offset, flex_regs[i], value); } + + CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, + gen8_make_rpcs(&INTEL_INFO(dev_priv)->sseu, sseu)); } /* @@ -1750,6 +1754,7 @@ static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_pr static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, const struct i915_oa_config *oa_config) { + struct intel_sseu default_sseu = intel_device_default_sseu(dev_priv); struct intel_engine_cs *engine = dev_priv->engine[RCS]; struct i915_gem_context *ctx; int ret; @@ -1795,7 +1800,8 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, ce->state->obj->mm.dirty = true; regs += LRC_STATE_PN * PAGE_SIZE / sizeof(*regs); - gen8_update_reg_state_unlocked(ctx, regs, oa_config); + gen8_update_reg_state_unlocked(ctx, regs, oa_config, + oa_config ? default_sseu : ce->sseu); i915_gem_object_unpin_map(ce->state->obj); } @@ -2167,14 +2173,21 @@ void i915_oa_init_reg_state(struct intel_engine_cs *engine, struct i915_gem_context *ctx, u32 *reg_state) { + struct drm_i915_private *i915 = engine->i915; struct i915_perf_stream *stream; if (engine->id != RCS) return; - stream = engine->i915->perf.oa.exclusive_stream; - if (stream) - gen8_update_reg_state_unlocked(ctx, reg_state, stream->oa_config); + stream = i915->perf.oa.exclusive_stream; + if (stream) { + struct intel_sseu default_sseu = + intel_device_default_sseu(i915); + + gen8_update_reg_state_unlocked(ctx, reg_state, + stream->oa_config, + default_sseu); + } } /** diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 8bac0483e784..7314e548fb4e 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2512,8 +2512,8 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine) return logical_ring_init(engine); } -static u32 make_rpcs(const struct sseu_dev_info *sseu, - struct intel_sseu ctx_sseu) +u32 gen8_make_rpcs(const struct sseu_dev_info *sseu, + struct intel_sseu ctx_sseu) { u32 rpcs = 0; @@ -2661,10 +2661,13 @@ static void execlists_init_reg_state(u32 *regs, } if (rcs) { + struct intel_sseu sseu = to_intel_context(ctx, engine)->sseu; + regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, - make_rpcs(&INTEL_INFO(dev_priv)->sseu, - to_intel_context(ctx, engine)->sseu)); + gen8_make_rpcs(&INTEL_INFO(dev_priv)->sseu, + intel_engine_prepare_sseu(engine, + sseu))); i915_oa_init_reg_state(engine, ctx, regs); } diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index 1593194e930c..6e6b2df95780 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -104,4 +104,7 @@ struct i915_gem_context; void intel_lr_context_resume(struct drm_i915_private *dev_priv); +u32 gen8_make_rpcs(const struct sseu_dev_info *sseu, + struct intel_sseu ctx_sseu); + #endif /* _INTEL_LRC_H_ */