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[134.134.139.75]) by smtp.gmail.com with ESMTPSA id 15-v6sm29079642pfq.81.2018.05.31.09.26.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 31 May 2018 09:26:24 -0700 (PDT) Date: Thu, 31 May 2018 09:26:17 -0700 From: Lucas De Marchi To: Jani Nikula Message-ID: <20180531162615.GA5200@ldmartin-desk.amr.corp.intel.com> References: <20180531115624.30269-1-jani.nikula@intel.com> <20180531115624.30269-2-jani.nikula@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20180531115624.30269-2-jani.nikula@intel.com> User-Agent: Mutt/1.9.5 (2018-04-13) Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915: fix guest virtual PCH detection on non-PCH systems X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP On Thu, May 31, 2018 at 02:56:21PM +0300, Jani Nikula wrote: > Virtualized non-PCH systems such as Broxton or Geminilake should use > PCH_NONE to indicate no PCH rather than PCH_NOP. The latter is a > specific case to indicate a PCH system without south display. Then let's go ahead and document it? ------------- Subject: [PATCH] drm/i915: document PCH_NOP There's a difference between PCH_NONE and PCH_NOP: the former means we don't have a PCH while in the latter we do, but it doesn't have the south display. Cc: Jani Nikula Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 72150f89f200..aa395a898258 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -631,7 +631,7 @@ enum intel_pch { PCH_KBP, /* Kaby Lake PCH */ PCH_CNP, /* Cannon Lake PCH */ PCH_ICP, /* Ice Lake PCH */ - PCH_NOP, + PCH_NOP, /* PCH without south display */ }; enum intel_sbi_destination {