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[5/6] drm/i915/gtt: Enable full-ppgtt by default for HSW

Message ID 20180601093554.13083-5-chris@chris-wilson.co.uk (mailing list archive)
State New, archived
Headers show

Commit Message

Chris Wilson June 1, 2018, 9:35 a.m. UTC
Let's see if we have all the kinks worked out and full-ppgtt now works
reliably on Haswell. If we can let userspace have full control over
their own ppgtt, it makes softpinning far more effective, in turn making
GPU dispatch far more efficient and more secure (due to better mm
segregation).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 992efe1881c8..371f509736b1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -179,7 +179,7 @@  int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 		return 0;
 	}
 
-	if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
+	if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) || IS_HASWELL(dev_priv)) {
 		if (has_full_48bit_ppgtt)
 			return 3;