diff mbox

[v3,05/12] drm/i915: Disallow plane scaling with specific pixel formats

Message ID 20180601170034.13095-6-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä June 1, 2018, 5 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Plane scaling is not supported with specific pixel formats. Disallow
plane scaling when such a format is used. Currently the only such
pixel format we expose is C8, but in case we add more in the future
let's make it easy to deal with them.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 drivers/gpu/drm/i915/intel_sprite.c  | 41 ++++++++++++++++++++++++------------
 3 files changed, 29 insertions(+), 15 deletions(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8b610c5498c0..10585c623508 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13101,7 +13101,7 @@  intel_check_primary_plane(struct intel_plane *plane,
 
 	if (INTEL_GEN(dev_priv) >= 9) {
 		/* use scaler when colorkey is not required */
-		if (!state->ckey.flags) {
+		if (!state->ckey.flags && intel_fb_scalable(state->base.fb)) {
 			min_scale = 1;
 			if (state->base.fb)
 				pixel_format = state->base.fb->format->format;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1b475744ab37..497b482b9c58 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2072,6 +2072,7 @@  bool intel_sdvo_init(struct drm_i915_private *dev_priv,
 
 /* intel_sprite.c */
 bool intel_format_is_yuv(u32 format);
+bool intel_fb_scalable(const struct drm_framebuffer *fb);
 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
 			     int usecs);
 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 01b0d28e69f8..22fb7ca5ae90 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -958,6 +958,19 @@  g4x_plane_get_hw_state(struct intel_plane *plane,
 	return ret;
 }
 
+bool intel_fb_scalable(const struct drm_framebuffer *fb)
+{
+	if (!fb)
+		return false;
+
+	switch (fb->format->format) {
+	case DRM_FORMAT_C8:
+		return false;
+	default:
+		return true;
+	}
+}
+
 static int
 intel_check_sprite_plane(struct intel_plane *plane,
 			 struct intel_crtc_state *crtc_state,
@@ -970,7 +983,6 @@  intel_check_sprite_plane(struct intel_plane *plane,
 	int max_scale, min_scale;
 	bool can_scale;
 	int ret;
-	uint32_t pixel_format = 0;
 
 	if (!fb) {
 		state->base.visible = false;
@@ -990,24 +1002,25 @@  intel_check_sprite_plane(struct intel_plane *plane,
 	}
 
 	/* setup can_scale, min_scale, max_scale */
+	can_scale = false;
+	min_scale = DRM_PLANE_HELPER_NO_SCALING;
+	max_scale = DRM_PLANE_HELPER_NO_SCALING;
+
 	if (INTEL_GEN(dev_priv) >= 9) {
-		if (state->base.fb)
-			pixel_format = state->base.fb->format->format;
 		/* use scaler when colorkey is not required */
-		if (!state->ckey.flags) {
-			can_scale = 1;
+		if (!state->ckey.flags && intel_fb_scalable(fb)) {
+			u32 pixel_format = fb ? fb->format->format : 0;
+
+			can_scale = true;
 			min_scale = 1;
-			max_scale =
-				skl_max_scale(crtc, crtc_state, pixel_format);
-		} else {
-			can_scale = 0;
-			min_scale = DRM_PLANE_HELPER_NO_SCALING;
-			max_scale = DRM_PLANE_HELPER_NO_SCALING;
+			max_scale = skl_max_scale(crtc, crtc_state, pixel_format);
 		}
 	} else {
-		can_scale = plane->can_scale;
-		max_scale = plane->max_downscale << 16;
-		min_scale = plane->can_scale ? 1 : (1 << 16);
+		if (intel_fb_scalable(fb)) {
+			can_scale = plane->can_scale;
+			max_scale = plane->max_downscale << 16;
+			min_scale = plane->can_scale ? 1 : (1 << 16);
+		}
 	}
 
 	ret = drm_atomic_helper_check_plane_state(&state->base,