From patchwork Mon Jun 4 14:19:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Piotr_Pi=C3=B3rkowski?= X-Patchwork-Id: 10446717 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4D5A860284 for ; Mon, 4 Jun 2018 14:22:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3D293291BE for ; Mon, 4 Jun 2018 14:22:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3AE8F29215; Mon, 4 Jun 2018 14:22:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A2A6D291BE for ; Mon, 4 Jun 2018 14:22:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7FFC36EB38; Mon, 4 Jun 2018 14:22:30 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id A16F16EB38 for ; Mon, 4 Jun 2018 14:22:29 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Jun 2018 07:22:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,476,1520924400"; d="scan'208";a="229774098" Received: from irsmsx105.ger.corp.intel.com ([163.33.3.28]) by orsmga005.jf.intel.com with ESMTP; 04 Jun 2018 07:22:28 -0700 Received: from localhost (172.28.172.32) by irsmsx105.ger.corp.intel.com (163.33.3.28) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 4 Jun 2018 15:22:26 +0100 From: Piotr Piorkowski To: Date: Mon, 4 Jun 2018 16:19:47 +0200 Message-ID: <20180604141947.8299-7-piotr.piorkowski@intel.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180604141947.8299-1-piotr.piorkowski@intel.com> References: <20180604141947.8299-1-piotr.piorkowski@intel.com> MIME-Version: 1.0 X-Originating-IP: [172.28.172.32] Subject: [Intel-gfx] [PATCH v2 7/7] drm/i915/guc: Add support for define guc_log_size in megabytes. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP At this moment we can define GuC logs sizes only using pages. But GuC also allows use for this values expressed in megabytes. Lets add support for define guc_log_size in megabytes when we debug of GuC. v2: - change buffers size to more friendly (Michał Wajdeczko) - merge statements in guc_ctl_log_params_flags() (Michał Wajdeczko) Signed-off-by: Piotr Piórkowski Cc: Michal Wajdeczko Cc: Michał Winiarski Cc: Joonas Lahtinen Cc: Chris Wilson Reviewed-by: Michal Wajdeczko --- drivers/gpu/drm/i915/intel_guc.c | 8 ++++++++ drivers/gpu/drm/i915/intel_guc_log.h | 6 ++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 68b94c23f26b..27a23f7ee4f8 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -263,7 +263,13 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc) u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT; u32 flags; + #if (((CRASH_BUFFER_SIZE) % (1 << 20)) == 0) + #define UNIT (1 << 20) + #define FLAG GUC_LOG_ALLOC_IN_MEGABYTE + #else #define UNIT (4 << 10) + #define FLAG 0 + #endif BUILD_BUG_ON(!CRASH_BUFFER_SIZE); BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, UNIT)); @@ -281,12 +287,14 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc) flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL | + FLAG | ((CRASH_BUFFER_SIZE / UNIT - 1) << GUC_LOG_CRASH_SHIFT) | ((DPC_BUFFER_SIZE / UNIT - 1) << GUC_LOG_DPC_SHIFT) | ((ISR_BUFFER_SIZE / UNIT - 1) << GUC_LOG_ISR_SHIFT) | (offset << GUC_LOG_BUF_ADDR_SHIFT); #undef UNIT + #undef FLAG return flags; } diff --git a/drivers/gpu/drm/i915/intel_guc_log.h b/drivers/gpu/drm/i915/intel_guc_log.h index 4ebb19f87b54..4feaeba1be1e 100644 --- a/drivers/gpu/drm/i915/intel_guc_log.h +++ b/drivers/gpu/drm/i915/intel_guc_log.h @@ -34,9 +34,15 @@ struct intel_guc; +#ifdef DRM_I915_DEBUG_GUC +#define CRASH_BUFFER_SIZE (2 * 1024 * 1024) +#define DPC_BUFFER_SIZE (8 * 1024 * 1024) +#define ISR_BUFFER_SIZE (8 * 1024 * 1024) +#else #define CRASH_BUFFER_SIZE (8 * 1024) #define DPC_BUFFER_SIZE (32 * 1024) #define ISR_BUFFER_SIZE (32 * 1024) +#endif /* * While we're using plain log level in i915, GuC controls are much more...