From patchwork Tue Jun 5 15:13:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Piotr_Pi=C3=B3rkowski?= X-Patchwork-Id: 10448477 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7316D6024A for ; Tue, 5 Jun 2018 15:13:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 62BC8296B4 for ; Tue, 5 Jun 2018 15:13:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 57212296E6; Tue, 5 Jun 2018 15:13:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 09BA2296B4 for ; Tue, 5 Jun 2018 15:13:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 572676EE1F; Tue, 5 Jun 2018 15:13:54 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id E85C46EE1F for ; Tue, 5 Jun 2018 15:13:52 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Jun 2018 08:13:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,479,1520924400"; d="scan'208";a="46933176" Received: from irsmsx105.ger.corp.intel.com ([163.33.3.28]) by orsmga008.jf.intel.com with ESMTP; 05 Jun 2018 08:13:51 -0700 Received: from localhost (172.28.172.32) by irsmsx105.ger.corp.intel.com (163.33.3.28) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 5 Jun 2018 16:13:50 +0100 From: Piotr Piorkowski To: Date: Tue, 5 Jun 2018 17:13:30 +0200 Message-ID: <20180605151330.9954-2-piotr.piorkowski@intel.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180604141947.8299-7-piotr.piorkowski@intel.com> References: <20180604141947.8299-7-piotr.piorkowski@intel.com> MIME-Version: 1.0 X-Originating-IP: [172.28.172.32] Subject: [Intel-gfx] [PATCH v3 7/7] drm/i915/guc: Add support for define guc_log_size in megabytes. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP At this moment we can define GuC logs sizes only using pages. But GuC also allows use for this values expressed in megabytes. Lets add support for define guc_log_size in megabytes when we debug of GuC. v2: - change buffers size to more friendly (Michał Wajdeczko) - merge statements in guc_ctl_log_params_flags() (Michał Wajdeczko) v3: - fix ifdef (rename DRM_I915_DEBUG_GUC to CONFIG_DRM_I915_DEBUG_GUC) (Michał Wajdeczko) - use SZ_* macros to define buffers sizes (Michał Wajdeczko) Signed-off-by: Piotr Piórkowski Cc: Michal Wajdeczko Cc: Michał Winiarski Cc: Joonas Lahtinen Cc: Chris Wilson Reviewed-by: Michal Wajdeczko --- drivers/gpu/drm/i915/intel_guc.c | 8 ++++++++ drivers/gpu/drm/i915/intel_guc_log.h | 6 ++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 915ef1b91146..8cf0a07a2df0 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -263,7 +263,13 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc) u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT; u32 flags; + #if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0) + #define UNIT SZ_1M + #define FLAG GUC_LOG_ALLOC_IN_MEGABYTE + #else #define UNIT SZ_4K + #define FLAG 0 + #endif BUILD_BUG_ON(!CRASH_BUFFER_SIZE); BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, UNIT)); @@ -281,12 +287,14 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc) flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL | + FLAG | ((CRASH_BUFFER_SIZE / UNIT - 1) << GUC_LOG_CRASH_SHIFT) | ((DPC_BUFFER_SIZE / UNIT - 1) << GUC_LOG_DPC_SHIFT) | ((ISR_BUFFER_SIZE / UNIT - 1) << GUC_LOG_ISR_SHIFT) | (offset << GUC_LOG_BUF_ADDR_SHIFT); #undef UNIT + #undef FLAG return flags; } diff --git a/drivers/gpu/drm/i915/intel_guc_log.h b/drivers/gpu/drm/i915/intel_guc_log.h index dfc07210a107..7bc763f10c03 100644 --- a/drivers/gpu/drm/i915/intel_guc_log.h +++ b/drivers/gpu/drm/i915/intel_guc_log.h @@ -34,9 +34,15 @@ struct intel_guc; +#ifdef CONFIG_DRM_I915_DEBUG_GUC +#define CRASH_BUFFER_SIZE SZ_2M +#define DPC_BUFFER_SIZE SZ_8M +#define ISR_BUFFER_SIZE SZ_8M +#else #define CRASH_BUFFER_SIZE SZ_8K #define DPC_BUFFER_SIZE SZ_32K #define ISR_BUFFER_SIZE SZ_32K +#endif /* * While we're using plain log level in i915, GuC controls are much more...