From patchwork Tue Jun 5 16:50:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10448649 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1F9C060234 for ; Tue, 5 Jun 2018 16:51:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1043829957 for ; Tue, 5 Jun 2018 16:51:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 049FB29961; Tue, 5 Jun 2018 16:51:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A076529957 for ; Tue, 5 Jun 2018 16:51:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C3D976E4B9; Tue, 5 Jun 2018 16:51:02 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id 44EE46E482 for ; Tue, 5 Jun 2018 16:50:59 +0000 (UTC) Received: by mail-wr0-x241.google.com with SMTP id 94-v6so3179425wrf.5 for ; Tue, 05 Jun 2018 09:50:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iQ9vpMa19vpH7A7fz5Z6eq1et2xqGn5Cd8pQIgI5018=; b=awMTdGnHEZzvsaFpC7KZPVIf8JPMH4Mc8XwrdOHvIK3+XmaNR2H7mqwVR7JV1xU/Ws RmiDNtNv/BA+9tQfr27lWbL0svdJp1h1+nuZW4tG9fgyOOWQzOqRH6Y6bTcH9jvV9Ic6 LB6snvVIBxd0hYHwCRRjXZosu7O5RSpqMiK4NUmsbroAR0CPkVE4RMxhxI65H8tr5Fhj 6nrgc1Bk4fkDxcRmWWrdxArF+dREUEsPGTyUqn8er/4wHMxZZ40Hnd2f77BLOFqnI9Sl wdAdIxfJWBh+0mXwN6bK5c1a4/a6pqlvNEjI+Lt5fv1WXWpKX9ZTvWaQStUrPQnPiW+H I5dg== X-Gm-Message-State: APt69E0eIwgEmmhAsYDGgQrRtAzdA47MCTFQDWOKCA7L5Uh2tZK8K2Fg EcDuQsNYPlz92iI2VxQ2vTr47g== X-Google-Smtp-Source: ADUXVKKRl369PfQxVS37mWkKonTZwKaOr2COp6LKIRiCdQOVddYh3Qp4SZPsG/4Gl4kla9V1lWPUeg== X-Received: by 2002:adf:a6b8:: with SMTP id t53-v6mr2752063wrc.45.1528217457953; Tue, 05 Jun 2018 09:50:57 -0700 (PDT) Received: from localhost.localdomain ([95.146.151.144]) by smtp.gmail.com with ESMTPSA id b14-v6sm38297918wrn.57.2018.06.05.09.50.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Jun 2018 09:50:57 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: igt-dev@lists.freedesktop.org Date: Tue, 5 Jun 2018 17:50:51 +0100 Message-Id: <20180605165051.29136-2-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180605165051.29136-1-tvrtko.ursulin@linux.intel.com> References: <20180605165051.29136-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH i-g-t 2/2] intel_gpu_overlay: Update for class:instance engine tracepoints X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin A miminal hack to parse the new tracepoint format and invent new "ring id's" based on engine class and instance. Signed-off-by: Tvrtko Ursulin Cc: Lionel Landwerlin --- overlay/gpu-perf.c | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/overlay/gpu-perf.c b/overlay/gpu-perf.c index ea3480050ab9..e77125672088 100644 --- a/overlay/gpu-perf.c +++ b/overlay/gpu-perf.c @@ -85,7 +85,8 @@ struct tracepoint { int device_field; int ctx_field; - int ring_field; + int class_field; + int instance_field; int seqno_field; int global_seqno_field; int plane_field; @@ -151,8 +152,10 @@ tracepoint_id(int tp_id) tp->device_field = f; } else if (!strcmp(tp->fields[f].name, "ctx")) { tp->ctx_field = f; - } else if (!strcmp(tp->fields[f].name, "ring")) { - tp->ring_field = f; + } else if (!strcmp(tp->fields[f].name, "class")) { + tp->class_field = f; + } else if (!strcmp(tp->fields[f].name, "instance")) { + tp->instance_field = f; } else if (!strcmp(tp->fields[f].name, "seqno")) { tp->seqno_field = f; } else if (!strcmp(tp->fields[f].name, "global_seqno")) { @@ -175,6 +178,23 @@ tracepoint_id(int tp_id) tracepoints[tp_id].fields[ \ tracepoints[tp_id].field_name##_field].offset)) +#define READ_TP_FIELD_U16(sample, tp_id, field_name) \ + (*(const uint16_t *)((sample)->tracepoint_data + \ + tracepoints[tp_id].fields[ \ + tracepoints[tp_id].field_name##_field].offset)) + +#define GET_RING_ID(sample, tp_id) \ +({ \ + unsigned char class, instance, ring; \ +\ + class = READ_TP_FIELD_U16(sample, tp_id, class); \ + instance = READ_TP_FIELD_U16(sample, tp_id, instance); \ +\ + ring = class * 2 + instance; \ +\ + ring; \ +}) + static int perf_tracepoint_open(struct gpu_perf *gp, int tp_id, int (*func)(struct gpu_perf *, const void *)) { @@ -313,7 +333,7 @@ static int request_add(struct gpu_perf *gp, const void *event) if (comm == NULL) return 0; - comm->nr_requests[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_ADD, ring)]++; + comm->nr_requests[GET_RING_ID(sample, TP_GEM_REQUEST_ADD)]++; return 1; } @@ -329,7 +349,7 @@ static int ctx_switch(struct gpu_perf *gp, const void *event) { const struct sample_event *sample = event; - gp->ctx_switch[READ_TP_FIELD_U32(sample, TP_GEM_RING_SWITCH_CONTEXT, ring)]++; + gp->ctx_switch[GET_RING_ID(sample, TP_GEM_RING_SWITCH_CONTEXT)]++; return 1; } @@ -367,8 +387,8 @@ static int wait_begin(struct gpu_perf *gp, const void *event) wait->context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ctx); wait->seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, seqno); wait->time = sample->time; - wait->next = gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)]; - gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)] = wait; + wait->next = gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)]; + gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)] = wait; return 0; } @@ -377,7 +397,7 @@ static int wait_end(struct gpu_perf *gp, const void *event) { const struct sample_event *sample = event; struct gpu_perf_time *wait, **prev; - uint32_t engine = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ring); + uint32_t engine = GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_END); uint32_t context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ctx); uint32_t seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, seqno);