| Message ID | 20180605201624.15604-1-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.17 next-20180605]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-gtt-Invalidate-GGTT-caches-after-writing-the-gen6-page-directories/20180607-003348
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x007-201822 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/i915_gem_gtt.c: In function 'gen6_write_page_range':
>> drivers/gpu/drm/i915/i915_gem_gtt.c:1747:28: error: 'struct i915_hw_ppgtt' has no member named 'vm'
gen6_ggtt_invalidate(ppgtt->vm.i915);
^~
drivers/gpu/drm/i915/i915_gem_gtt.c: In function 'gen6_alloc_va_range':
drivers/gpu/drm/i915/i915_gem_gtt.c:1963:29: error: 'struct i915_hw_ppgtt' has no member named 'vm'
gen6_ggtt_invalidate(ppgtt->vm.i915);
^~
vim +1747 drivers/gpu/drm/i915/i915_gem_gtt.c
1734
1735 /* Write all the page tables found in the ppgtt structure to incrementing page
1736 * directories. */
1737 static void gen6_write_page_range(struct i915_hw_ppgtt *ppgtt,
1738 u32 start, u32 length)
1739 {
1740 struct i915_page_table *pt;
1741 unsigned int pde;
1742
1743 gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde)
1744 gen6_write_pde(ppgtt, pde, pt);
1745
1746 mark_tlbs_dirty(ppgtt);
> 1747 gen6_ggtt_invalidate(ppgtt->vm.i915);
1748 }
1749
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 163c71784014..b232452ff5b9 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1687,8 +1687,8 @@ static inline void gen6_write_pde(const struct i915_hw_ppgtt *ppgtt, const struct i915_page_table *pt) { /* Caller needs to make sure the write completes if necessary */ - writel_relaxed(GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID, - ppgtt->pd_addr + pde); + iowrite32(GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID, + ppgtt->pd_addr + pde); } /* Write all the page tables found in the ppgtt structure to incrementing page @@ -1703,7 +1703,7 @@ static void gen6_write_page_range(struct i915_hw_ppgtt *ppgtt, gen6_write_pde(ppgtt, pde, pt); mark_tlbs_dirty(ppgtt); - wmb(); + gen6_ggtt_invalidate(ppgtt->vm.i915); } static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt) @@ -1919,7 +1919,7 @@ static int gen6_alloc_va_range(struct i915_address_space *vm, if (flush) { mark_tlbs_dirty(ppgtt); - wmb(); + gen6_ggtt_invalidate(ppgtt->vm.i915); } return 0;
When we update the gen6 ppgtt page directories, we do so by writing the new address into a reserved slot in the GGTT. It appears that when the GPU reads that entry from the gsm, it uses its small cache and that we need to invalidate that cache after writing. We don't see an issue currently as we prefill the ppgtt page directories on creation; and only create the single aliasing_ppgtt long before we start using the GGTT (and so before the cache mayhave a conflicting entry). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)