From patchwork Wed Jun 6 12:48:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10450183 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B60DF60375 for ; Wed, 6 Jun 2018 12:50:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A6A5D29A22 for ; Wed, 6 Jun 2018 12:50:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A4C5529C26; Wed, 6 Jun 2018 12:50:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 252EE29D6F for ; Wed, 6 Jun 2018 12:48:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 331AA6E69B; Wed, 6 Jun 2018 12:48:58 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id CDB356E68D for ; Wed, 6 Jun 2018 12:48:55 +0000 (UTC) Received: by mail-wm0-x243.google.com with SMTP id x6-v6so11241788wmc.3 for ; Wed, 06 Jun 2018 05:48:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Yld5q3wbf9D7UkPU1kctHcW7vWSIgoDamNaiNh+lqy8=; b=ajEIUh0raAxw4Hdz00t1TbjVtv0NcL6Sbrr0dqDTgYxWKhqYceZz6PLyERCRViMmvV zXVyZAKY8dkOtkCVLSSrU9fomaS3kAZzzjUumabjfC3j7nAKBOt2B6pj+i0H8XgIH7R0 ktEC1S8GGI0gbWKoLYhyoMelVOXGg5la9yjPwKJ4+SbkdbDkhcAjjcS98rr1jxwzAqKe PX2I65uhUQK6H/2NiIV01WTKwuAr3ruFzuGw/gHjPN8WqIRXfLtGW98q8oJ2P3rITETg NNbvxGUw5hrtrpRKb0yXNhmTNd4G424CRQfXup5U1Je8vfYR7tnYpFTDJrN7N86LcGrX nhCA== X-Gm-Message-State: APt69E0cHVsw6fXQySUuZDm9wVpAoL8V2oaDhddaLFaW5Kn8byoSNZSc GSnRXWaR5bW+R8fh71GBhtQ2WHW1 X-Google-Smtp-Source: ADUXVKKBgZTFTKAfemtav905sVusZUHQojEI2WShmxFmmOSJspayRdV1cG0pL1zM//SxL2ZMabFScg== X-Received: by 2002:a1c:b7d4:: with SMTP id h203-v6mr1628879wmf.161.1528289334351; Wed, 06 Jun 2018 05:48:54 -0700 (PDT) Received: from localhost.localdomain ([95.146.151.144]) by smtp.gmail.com with ESMTPSA id v14-v6sm24982999wro.33.2018.06.06.05.48.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Jun 2018 05:48:53 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Wed, 6 Jun 2018 13:48:42 +0100 Message-Id: <20180606124848.13050-2-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180606124848.13050-1-tvrtko.ursulin@linux.intel.com> References: <20180606124848.13050-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH 1/7] drm/i915/pmu: Fix enable count array size and bounds checking X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Enable count array is supposed to have one counter for each possible engine sampler. As such array sizing and bounds checking is not correct when more engine samplers are added. At the same time tidy the assert for readability and robustness. Signed-off-by: Tvrtko Ursulin Fixes: b46a33e271ed ("drm/i915/pmu: Expose a PMU interface for perf queries") Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_pmu.c | 13 +++++++++---- drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index c39541ed2219..b8c6953867ee 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -593,7 +593,8 @@ static void i915_pmu_enable(struct perf_event *event) * Update the bitmask of enabled events and increment * the event reference counter. */ - GEM_BUG_ON(bit >= I915_PMU_MASK_BITS); + BUILD_BUG_ON(ARRAY_SIZE(i915->pmu.enable_count) != I915_PMU_MASK_BITS); + GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count)); GEM_BUG_ON(i915->pmu.enable_count[bit] == ~0); i915->pmu.enable |= BIT_ULL(bit); i915->pmu.enable_count[bit]++; @@ -617,7 +618,10 @@ static void i915_pmu_enable(struct perf_event *event) GEM_BUG_ON(!engine); engine->pmu.enable |= BIT(sample); - GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS); + BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) != + (1 << I915_PMU_SAMPLE_BITS)); + GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count)); + GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample)); GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0); engine->pmu.enable_count[sample]++; } @@ -649,7 +653,8 @@ static void i915_pmu_disable(struct perf_event *event) engine_event_class(event), engine_event_instance(event)); GEM_BUG_ON(!engine); - GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS); + GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count)); + GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample)); GEM_BUG_ON(engine->pmu.enable_count[sample] == 0); /* * Decrement the reference count and clear the enabled @@ -659,7 +664,7 @@ static void i915_pmu_disable(struct perf_event *event) engine->pmu.enable &= ~BIT(sample); } - GEM_BUG_ON(bit >= I915_PMU_MASK_BITS); + GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count)); GEM_BUG_ON(i915->pmu.enable_count[bit] == 0); /* * Decrement the reference count and clear the enabled diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index acef385c4c80..2f3232599d80 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -397,7 +397,7 @@ struct intel_engine_cs { * * Index number corresponds to the bit number from @enable. */ - unsigned int enable_count[I915_PMU_SAMPLE_BITS]; + unsigned int enable_count[1 << I915_PMU_SAMPLE_BITS]; /** * @sample: Counter values for sampling events. *