From patchwork Wed Jun 6 12:48:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10450165 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7A36060146 for ; Wed, 6 Jun 2018 12:50:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6B30329D32 for ; Wed, 6 Jun 2018 12:50:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5F52029C26; Wed, 6 Jun 2018 12:50:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 19D9229CAE for ; Wed, 6 Jun 2018 12:49:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6180E6EFF4; Wed, 6 Jun 2018 12:49:04 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id 182416EFEE for ; Wed, 6 Jun 2018 12:49:02 +0000 (UTC) Received: by mail-wr0-x243.google.com with SMTP id 94-v6so6159817wrf.5 for ; Wed, 06 Jun 2018 05:49:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TH7ruDuEgIetLkMlMq5KDfMTjW0zMSDKYw28I/fhMGI=; b=a3H+jDanRhFcKAUV7sos1hRJSLrK7OW5O2XxDIbi204scSaI8bTQ8fgba8BmThznUv C/K+uYLOQAWyVJdq6JLUC/ZMiESozsiKxI4f5JWrMJUoVEUt0yQI+17P71rn8RzdCqBk aqmjVU9X7lApuD9afUvYHLGSoAzhhH7hzzalLoglO+MJppiy1W7Hq/JXSwiV5BLVtnOW oXUNw9YZFJhk5p/H8ySXOt53VV5ZG+7QOLriiOCO6dPRbDDiM5ehoal/0aKRnHISdWeY rDyYsFeZ3vf+sfWpKyyqYiqhkNTvJoZxRJWGgWTyAITpTWbzGqK5NrNph+U/BqM90EQo wKvw== X-Gm-Message-State: APt69E1GDii3e/qCNxvLyojaFTGIjglYLvUdT8sAkEFhptkcPsbrpfEc znSX/VOl658HEnWl6QEfzCkdJXHT X-Google-Smtp-Source: ADUXVKLoqZQoOeO4gxBBLBn3eME24nvudPQYW+I15PaDelBovP27HkMrGB8CmyDJ6lUJmXvLkC5jAw== X-Received: by 2002:adf:c907:: with SMTP id m7-v6mr2460899wrh.6.1528289340615; Wed, 06 Jun 2018 05:49:00 -0700 (PDT) Received: from localhost.localdomain ([95.146.151.144]) by smtp.gmail.com with ESMTPSA id v14-v6sm24982999wro.33.2018.06.06.05.48.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Jun 2018 05:49:00 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Wed, 6 Jun 2018 13:48:48 +0100 Message-Id: <20180606124848.13050-8-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180606124848.13050-1-tvrtko.ursulin@linux.intel.com> References: <20180606124848.13050-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH 7/7] drm/i915: Engine queues query X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin As well as exposing active requests on engines via PMU, we can also export the current raw values (as tracked by i915 command submission) via a dedicated query. This is to satisfy customers who have userspace load balancing solutions implemented on top of their custom kernel patches. Userspace is now able to include DRM_I915_QUERY_ENGINE_QUEUES in their query list, pointing to initialized struct drm_i915_query_engine_queues entry. Fields describing engine class and instance userspace would like to know about need to be filled in, and i915 will fill in the rest. Multiple engines can be queried in one go by having multiple queries in the query list. v2: * Use EINVAL for reporting insufficient buffer space. (Chris Wilson) v3: * One more reserved dword because I like even numbers. Lionel Landwerlin: * Document input fields. * Document reserved bits must be zero. Signed-off-by: Tvrtko Ursulin Cc: Dmitry Rogozhkin Reviewed-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_query.c | 43 +++++++++++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 29 +++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index 3f502eef2431..6a01c1c58f4f 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -84,9 +84,52 @@ static int query_topology_info(struct drm_i915_private *dev_priv, return total_length; } +static int +query_engine_queues(struct drm_i915_private *i915, + struct drm_i915_query_item *query_item) +{ + struct drm_i915_query_engine_queues __user *query_ptr = + u64_to_user_ptr(query_item->data_ptr); + struct drm_i915_query_engine_queues query; + struct intel_engine_cs *engine; + const int len = sizeof(query); + unsigned int i; + + if (query_item->flags) + return -EINVAL; + + if (!query_item->length) + return len; + else if (query_item->length < len) + return -EINVAL; + + if (copy_from_user(&query, query_ptr, len)) + return -EFAULT; + + for (i = 0; i < ARRAY_SIZE(query.rsvd); i++) { + if (query.rsvd[i]) + return -EINVAL; + } + + engine = intel_engine_lookup_user(i915, query.class, query.instance); + if (!engine) + return -ENOENT; + + query.queued = atomic_read(&engine->request_stats.queued); + query.runnable = engine->request_stats.runnable; + query.running = intel_engine_last_submit(engine) - + intel_engine_get_seqno(engine); + + if (copy_to_user(query_ptr, &query, len)) + return -EFAULT; + + return len; +} + static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, struct drm_i915_query_item *query_item) = { query_topology_info, + query_engine_queues, }; int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 9a00c30e4071..c82035b71824 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1637,6 +1637,7 @@ struct drm_i915_perf_oa_config { struct drm_i915_query_item { __u64 query_id; #define DRM_I915_QUERY_TOPOLOGY_INFO 1 +#define DRM_I915_QUERY_ENGINE_QUEUES 2 /* * When set to zero by userspace, this is filled with the size of the @@ -1734,6 +1735,34 @@ struct drm_i915_query_topology_info { __u8 data[]; }; +/** + * struct drm_i915_query_engine_queues + * + * Engine queues query enables userspace to query current counts of active + * requests in their different states. + */ +struct drm_i915_query_engine_queues { + /** + * Engine class as in enum drm_i915_gem_engine_class (set by userspace). + */ + __u16 class; + + /** Engine instance number (set by userspace). */ + __u16 instance; + + /** Number of requests with unresolved fences and dependencies. */ + __u32 queued; + + /** Number of ready requests waiting on a slot on GPU. */ + __u32 runnable; + + /** Number of requests executing on the GPU. */ + __u32 running; + + /** Reserved bits must be set to zero by userspace. */ + __u32 rsvd[6]; +}; + #if defined(__cplusplus) } #endif