| Message ID | 20180607161353.21078-1-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Jun 07, 2018 at 07:13:53PM +0300, Imre Deak wrote: > While checking workarounds related to the CDCLK PLL, I noticed that the > DMC firmware bits for WA#1183 are missing for SKL. After that I > clarified with HW people that it's not needed on SKL, since it doesn't > support eDP1.4 which would be the only thing requiring the problematic > CDCLK clock rates. So in theory we shouldn't ever choose these > frequencies, but add an assert in any case for catching such cases and > for documentation. > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/intel_cdclk.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c > index 704ddb4d3ca7..71045c38e233 100644 > --- a/drivers/gpu/drm/i915/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > @@ -2355,6 +2355,16 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) > */ > cdclk = skl_calc_cdclk(min_cdclk, vco); > > + /* > + * The following CDCLK rates are unsupported on SKL. In theory this > + * should never happen since only the eDP1.4 2.16 and 4.32Gbps rates > + * require it, but eDP1.4 is not supported on SKL, see display > + * WA#1183. > + */ > + if (IS_SKYLAKE(to_i915(state->dev)) && > + (cdclk == 308571 || cdclk == 617143)) > + DRM_WARN_ONCE("Unsupported CDCLK rate.\n"); Or just WARN(vco == 8640000) in eg. skl_set_cdclk()? > + > intel_state->cdclk.logical.vco = vco; > intel_state->cdclk.logical.cdclk = cdclk; > intel_state->cdclk.logical.voltage_level = > -- > 2.13.2
On Thu, Jun 07, 2018 at 08:01:14PM +0300, Ville Syrjälä wrote: > On Thu, Jun 07, 2018 at 07:13:53PM +0300, Imre Deak wrote: > > While checking workarounds related to the CDCLK PLL, I noticed that the > > DMC firmware bits for WA#1183 are missing for SKL. After that I > > clarified with HW people that it's not needed on SKL, since it doesn't > > support eDP1.4 which would be the only thing requiring the problematic > > CDCLK clock rates. So in theory we shouldn't ever choose these > > frequencies, but add an assert in any case for catching such cases and > > for documentation. > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > --- > > drivers/gpu/drm/i915/intel_cdclk.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c > > index 704ddb4d3ca7..71045c38e233 100644 > > --- a/drivers/gpu/drm/i915/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > > @@ -2355,6 +2355,16 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) > > */ > > cdclk = skl_calc_cdclk(min_cdclk, vco); > > > > + /* > > + * The following CDCLK rates are unsupported on SKL. In theory this > > + * should never happen since only the eDP1.4 2.16 and 4.32Gbps rates > > + * require it, but eDP1.4 is not supported on SKL, see display > > + * WA#1183. > > + */ > > + if (IS_SKYLAKE(to_i915(state->dev)) && > > + (cdclk == 308571 || cdclk == 617143)) > > + DRM_WARN_ONCE("Unsupported CDCLK rate.\n"); > > Or just WARN(vco == 8640000) in eg. skl_set_cdclk()? Ok, can move it there. cdclk==432MHz is not specifically disallowed, so wouldn't checking cdclk be clearer? Even if it's not used atm. > > + > > intel_state->cdclk.logical.vco = vco; > > intel_state->cdclk.logical.cdclk = cdclk; > > intel_state->cdclk.logical.voltage_level = > > -- > > 2.13.2 > > -- > Ville Syrjälä > Intel
On Fri, Jun 08, 2018 at 06:44:38PM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/icl: Add warn about unsupported CDCLK rates (rev3) > URL : https://patchwork.freedesktop.org/series/44421/ > State : success Pushed to -dinq, thanks for the review. > > == Summary == > > = CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9244_full = > > == Summary - WARNING == > > Minor unknown changes coming with Patchwork_9244_full need to be verified > manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_9244_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > == Possible new issues == > > Here are the unknown changes that may have been introduced in Patchwork_9244_full: > > === IGT changes === > > ==== Warnings ==== > > igt@gem_exec_schedule@deep-bsd1: > shard-kbl: PASS -> SKIP +1 > > igt@perf_pmu@rc6: > shard-kbl: SKIP -> PASS > > > == Known issues == > > Here are the changes found in Patchwork_9244_full that come from known issues: > > === IGT changes === > > ==== Issues hit ==== > > igt@drv_selftest@live_hangcheck: > shard-apl: PASS -> DMESG-FAIL (fdo#106560) > > igt@kms_flip@2x-flip-vs-expired-vblank: > shard-hsw: PASS -> FAIL (fdo#105189) > > igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: > shard-glk: PASS -> FAIL (fdo#105363) > > igt@kms_flip@flip-vs-expired-vblank-interruptible: > shard-glk: PASS -> FAIL (fdo#105189) > > igt@kms_flip@plain-flip-ts-check-interruptible: > shard-glk: PASS -> FAIL (fdo#100368) > > igt@kms_setmode@basic: > shard-apl: PASS -> FAIL (fdo#99912) > > > ==== Possible fixes ==== > > igt@drv_selftest@live_gtt: > shard-glk: INCOMPLETE (fdo#103359, k.org#198133) -> PASS > shard-apl: FAIL (fdo#105347) -> PASS > > igt@drv_selftest@live_hangcheck: > shard-kbl: DMESG-FAIL (fdo#106560) -> PASS > > igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: > shard-glk: FAIL (fdo#105703) -> PASS > > igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: > shard-glk: FAIL (fdo#105454, fdo#106509) -> PASS > > igt@kms_flip@2x-plain-flip-fb-recreate: > shard-hsw: FAIL (fdo#100368) -> PASS +1 > shard-glk: FAIL (fdo#100368) -> PASS > > igt@kms_flip@modeset-vs-vblank-race-interruptible: > shard-hsw: FAIL (fdo#103060) -> PASS +1 > > igt@kms_flip_tiling@flip-to-y-tiled: > shard-glk: FAIL (fdo#104724) -> PASS > > igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: > shard-snb: FAIL (fdo#103167, fdo#104724) -> PASS > > > fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 > fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 > fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 > fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 > fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 > fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189 > fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 > fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 > fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 > fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 > fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 > fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 > fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 > k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 > > > == Participating hosts (5 -> 5) == > > No changes in participating hosts > > > == Build changes == > > * Linux: CI_DRM_4294 -> Patchwork_9244 > > CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_9244: 38bcd836f3574fc1949555dc0cb11e8a9ad25c82 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9244/shards.html
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 704ddb4d3ca7..71045c38e233 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -2355,6 +2355,16 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) */ cdclk = skl_calc_cdclk(min_cdclk, vco); + /* + * The following CDCLK rates are unsupported on SKL. In theory this + * should never happen since only the eDP1.4 2.16 and 4.32Gbps rates + * require it, but eDP1.4 is not supported on SKL, see display + * WA#1183. + */ + if (IS_SKYLAKE(to_i915(state->dev)) && + (cdclk == 308571 || cdclk == 617143)) + DRM_WARN_ONCE("Unsupported CDCLK rate.\n"); + intel_state->cdclk.logical.vco = vco; intel_state->cdclk.logical.cdclk = cdclk; intel_state->cdclk.logical.voltage_level =
While checking workarounds related to the CDCLK PLL, I noticed that the DMC firmware bits for WA#1183 are missing for SKL. After that I clarified with HW people that it's not needed on SKL, since it doesn't support eDP1.4 which would be the only thing requiring the problematic CDCLK clock rates. So in theory we shouldn't ever choose these frequencies, but add an assert in any case for catching such cases and for documentation. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/intel_cdclk.c | 10 ++++++++++ 1 file changed, 10 insertions(+)