| Message ID | 20180608140002.6795-1-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jun 08, 2018 at 05:00:02PM +0300, Imre Deak wrote: > While checking workarounds related to the CDCLK PLL, I noticed that the > DMC firmware bits for WA#1183 are missing for SKL. After that I > clarified with HW people that it's not needed on SKL, since it doesn't > support eDP1.4 which would be the only thing requiring the problematic > CDCLK clock rates. So in theory we shouldn't ever choose these > frequencies, but add an assert in any case for catching such cases and > for documentation. > > v2: > - Move the check to skl_set_cdclk and warn whenever using the > corresponding VCO freq. (Ville) > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/intel_cdclk.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c > index 704ddb4d3ca7..a1e9434698b9 100644 > --- a/drivers/gpu/drm/i915/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > @@ -991,6 +991,16 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, > u32 freq_select, cdclk_ctl; > int ret; > > + /* > + * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are > + * unsupported on SKL. In theory this should never happen since only > + * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not > + * supported on SKL either, see the above WA. WARN whenever trying to > + * use the corresponding VCO freq as that always leads to using the > + * minimum 308MHz CDCLK. > + */ > + WARN_ON_ONCE(vco == 8640000); Needs IS_SKYLAKE() with that Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > + > mutex_lock(&dev_priv->pcu_lock); > ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, > SKL_CDCLK_PREPARE_FOR_CHANGE, > -- > 2.13.2
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 704ddb4d3ca7..a1e9434698b9 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -991,6 +991,16 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, u32 freq_select, cdclk_ctl; int ret; + /* + * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are + * unsupported on SKL. In theory this should never happen since only + * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not + * supported on SKL either, see the above WA. WARN whenever trying to + * use the corresponding VCO freq as that always leads to using the + * minimum 308MHz CDCLK. + */ + WARN_ON_ONCE(vco == 8640000); + mutex_lock(&dev_priv->pcu_lock); ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, SKL_CDCLK_PREPARE_FOR_CHANGE,
While checking workarounds related to the CDCLK PLL, I noticed that the DMC firmware bits for WA#1183 are missing for SKL. After that I clarified with HW people that it's not needed on SKL, since it doesn't support eDP1.4 which would be the only thing requiring the problematic CDCLK clock rates. So in theory we shouldn't ever choose these frequencies, but add an assert in any case for catching such cases and for documentation. v2: - Move the check to skl_set_cdclk and warn whenever using the corresponding VCO freq. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/intel_cdclk.c | 10 ++++++++++ 1 file changed, 10 insertions(+)