diff mbox

[v4,3/5] drm/i915/psr: Handle PSR RFB storage error

Message ID 20180614203433.5602-3-jose.souza@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Souza, Jose June 14, 2018, 8:34 p.m. UTC 
Sink will interrupt source when it have any problem saving or reading
the remote frame buffer.

v3:
disabling PSR instead of exiting on error

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index af5fcfd98a53..fd240e45f341 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1026,6 +1026,20 @@  void intel_psr_short_pulse(struct intel_dp *intel_dp)
 		psr_disable(intel_dp);
 	}
 
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
+		DRM_ERROR("PSR_ERROR_STATUS dpcd read failed\n");
+		goto exit;
+	}
+
+	if (val & DP_PSR_RFB_STORAGE_ERROR) {
+		DRM_DEBUG_KMS("PSR RFB storage error, exiting PSR\n");
+		psr_disable(intel_dp);
+	}
+	if (val & (DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | DP_PSR_LINK_CRC_ERROR))
+		DRM_ERROR("PSR_ERROR_STATUS not handled %x\n", val);
+	/* clear status register */
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
+
 	/* TODO: handle other PSR/PSR2 errors */
 exit:
 	mutex_unlock(&psr->lock);