From patchwork Thu Jun 14 21:53:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kenneth Graunke X-Patchwork-Id: 10465381 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6DAFB60348 for ; Thu, 14 Jun 2018 22:03:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4F81328B1E for ; Thu, 14 Jun 2018 22:03:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 41DCB28905; Thu, 14 Jun 2018 22:03:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DD80B28905 for ; Thu, 14 Jun 2018 22:03:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BA9996E90D; Thu, 14 Jun 2018 22:03:09 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org X-Greylist: delayed 573 seconds by postgrey-1.36 at gabe; Thu, 14 Jun 2018 22:03:07 UTC Received: from smtp65.iad3a.emailsrvr.com (smtp65.iad3a.emailsrvr.com [173.203.187.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id D433D6E90D for ; Thu, 14 Jun 2018 22:03:07 +0000 (UTC) Received: from smtp25.relay.iad3a.emailsrvr.com (localhost [127.0.0.1]) by smtp25.relay.iad3a.emailsrvr.com (SMTP Server) with ESMTP id 4D2F72523D; Thu, 14 Jun 2018 17:53:34 -0400 (EDT) X-Auth-ID: kenneth@whitecape.org Received: by smtp25.relay.iad3a.emailsrvr.com (Authenticated sender: kenneth-AT-whitecape.org) with ESMTPSA id CC4052398A; Thu, 14 Jun 2018 17:53:33 -0400 (EDT) X-Sender-Id: kenneth@whitecape.org Received: from kirito.localdomain ([UNAVAILABLE]. [134.134.139.92]) (using TLSv1.2 with cipher DHE-RSA-AES128-GCM-SHA256) by 0.0.0.0:465 (trex/5.7.12); Thu, 14 Jun 2018 17:53:34 -0400 From: Kenneth Graunke To: intel-gfx@lists.freedesktop.org Date: Thu, 14 Jun 2018 14:53:28 -0700 Message-Id: <20180614215328.2182-1-kenneth@whitecape.org> X-Mailer: git-send-email 2.17.0 Subject: [Intel-gfx] [PATCH] drm/i915: Enable provoking vertex fix on Gen9+ systems. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kenneth Graunke MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The SF and clipper units mishandle the provoking vertex in some cases, which can cause misrendering with shaders that use flat shaded inputs. There are chicken bits in 3D_CHICKEN3 (for SF) and FF_SLICE_CHICKEN (for the clipper) that work around the issue. These registers are unfortunately not part of the logical context (even the power context). This patch sets both bits, and bumps the number of allowed workaround registers to avoid running out of space (thanks to Chris Wilson for helping debug that issue). I am not aware of any workaround names or numbers assigned for these issues, they're simply recommended in the documentation for each of the registers. Bugzilla: https://bugs.freedesktop.org/103047 --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 19defe73b156..8828780a1773 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1309,7 +1309,7 @@ struct i915_wa_reg { u32 mask; }; -#define I915_MAX_WA_REGS 16 +#define I915_MAX_WA_REGS 17 struct i915_workarounds { struct i915_wa_reg reg[I915_MAX_WA_REGS]; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 140f6a27d696..35d8c2be85be 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2432,12 +2432,17 @@ enum i915_power_well_id { #define _3D_CHICKEN _MMIO(0x2084) #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) #define _3D_CHICKEN2 _MMIO(0x208c) + +#define FF_SLICE_CHICKEN _MMIO(0x2088) +#define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1) + /* Disables pipelining of read flushes past the SF-WIZ interface. * Required on all Ironlake steppings according to the B-Spec, but the * particular danger of not doing so is not specified. */ # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) #define _3D_CHICKEN3 _MMIO(0x2090) +#define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12) #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5) #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 24b929ce3341..2dea23bfd5ea 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -274,6 +274,12 @@ static int gen9_ctx_workarounds_init(struct drm_i915_private *dev_priv) if (IS_GEN9_LP(dev_priv)) WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); + /* BSpec: 11391 */ + WA_SET_BIT_MASKED(FF_SLICE_CHICKEN, + FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX); + /* BSpec: 11299 */ + WA_SET_BIT_MASKED(_3D_CHICKEN3, _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX); + return 0; }