From patchwork Mon Jul 2 09:07:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 10500725 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A4B916028F for ; Mon, 2 Jul 2018 09:07:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 944A828555 for ; Mon, 2 Jul 2018 09:07:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9299D28565; Mon, 2 Jul 2018 09:07:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 29C24285FF for ; Mon, 2 Jul 2018 09:07:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 452DC6E35C; Mon, 2 Jul 2018 09:07:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id 387B96E353; Mon, 2 Jul 2018 09:07:51 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 12222469-1500050 for multiple; Mon, 02 Jul 2018 10:07:31 +0100 From: Chris Wilson To: igt-dev@lists.freedesktop.org Date: Mon, 2 Jul 2018 10:07:27 +0100 Message-Id: <20180702090727.7721-17-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180702090727.7721-1-chris@chris-wilson.co.uk> References: <20180702090727.7721-1-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH i-g-t 17/17] igt/gem_exec_latency: Robustify measurements X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Repeat the latency measurements and present the median over many so that the results are more reliable. Signed-off-by: Chris Wilson --- tests/gem_exec_latency.c | 165 ++++++++++++++++++--------------------- 1 file changed, 75 insertions(+), 90 deletions(-) diff --git a/tests/gem_exec_latency.c b/tests/gem_exec_latency.c index de16322a6..c2fdf7ee2 100644 --- a/tests/gem_exec_latency.c +++ b/tests/gem_exec_latency.c @@ -258,13 +258,12 @@ static void latency_from_ring(int fd, const int gen = intel_gen(intel_get_drm_devid(fd)); const int has_64bit_reloc = gen >= 8; struct drm_i915_gem_exec_object2 obj[3]; - struct drm_i915_gem_relocation_entry reloc; struct drm_i915_gem_execbuffer2 execbuf; - const unsigned int repeats = ring_size / 2; + uint64_t presumed_offset; unsigned int other; uint32_t *map, *results; uint32_t ctx[2] = {}; - int i, j; + int j; if (flags & PREEMPT) { ctx[0] = gem_context_create(fd); @@ -294,102 +293,83 @@ static void latency_from_ring(int fd, map[0] = MI_BATCH_BUFFER_END; gem_execbuf(fd, &execbuf); - memset(&reloc,0, sizeof(reloc)); - obj[2].relocation_count = 1; - obj[2].relocs_ptr = to_user_pointer(&reloc); - gem_set_domain(fd, obj[2].handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT); + presumed_offset = obj[1].offset; + for (j = 0; j < 1024; j++) { + uint64_t offset = sizeof(uint32_t) * j + presumed_offset; + int i = 16 * j; - reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION; - reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION; - reloc.presumed_offset = obj[1].offset; - reloc.target_handle = flags & CORK ? 1 : 0; + /* MI_STORE_REG_MEM */ + map[i++] = 0x24 << 23 | 1; + if (has_64bit_reloc) + map[i-1]++; + map[i++] = RCS_TIMESTAMP; /* ring local! */ + map[i++] = offset; + if (has_64bit_reloc) + map[i++] = offset >> 32; + + map[i++] = MI_BATCH_BUFFER_END; + } + igt_assert(ring_size <= 1024); for_each_physical_engine(fd, other) { - igt_spin_t *spin = NULL; - IGT_CORK_HANDLE(c); - - gem_set_domain(fd, obj[2].handle, - I915_GEM_DOMAIN_GTT, - I915_GEM_DOMAIN_GTT); - - if (flags & PREEMPT) - spin = __igt_spin_batch_new(fd, - .ctx = ctx[0], - .engine = ring); - - if (flags & CORK) { - obj[0].handle = igt_cork_plug(&c, fd); - execbuf.buffers_ptr = to_user_pointer(&obj[0]); - execbuf.buffer_count = 3; - } + if (flags & PREEMPT && other == ring) + continue; + + for (int qlen = 1; qlen < ring_size/2; qlen *= 2) { + unsigned int count = 32 * ring_size / qlen; + igt_stats_t stats; + + igt_stats_init_with_size(&stats, count); + for (unsigned int rep = 0; rep < count; rep++) { + igt_spin_t *spin = NULL; + IGT_CORK_HANDLE(c); + + if (flags & PREEMPT) + spin = __igt_spin_batch_new(fd, + .ctx = ctx[0], + .engine = ring); + + if (flags & CORK) { + obj[0].handle = igt_cork_plug(&c, fd); + execbuf.buffers_ptr = to_user_pointer(&obj[0]); + execbuf.buffer_count = 3; + } - for (j = 0; j < repeats; j++) { - uint64_t offset; - - execbuf.flags &= ~ENGINE_FLAGS; - execbuf.flags |= ring; - - execbuf.batch_start_offset = 64 * j; - reloc.offset = - execbuf.batch_start_offset + sizeof(uint32_t); - reloc.delta = sizeof(uint32_t) * j; - - reloc.presumed_offset = obj[1].offset; - offset = reloc.presumed_offset; - offset += reloc.delta; - - i = 16 * j; - /* MI_STORE_REG_MEM */ - map[i++] = 0x24 << 23 | 1; - if (has_64bit_reloc) - map[i-1]++; - map[i++] = RCS_TIMESTAMP; /* ring local! */ - map[i++] = offset; - if (has_64bit_reloc) - map[i++] = offset >> 32; - map[i++] = MI_BATCH_BUFFER_END; - - gem_execbuf(fd, &execbuf); - - execbuf.flags &= ~ENGINE_FLAGS; - execbuf.flags |= other; - - execbuf.batch_start_offset = 64 * (j + repeats); - reloc.offset = - execbuf.batch_start_offset + sizeof(uint32_t); - reloc.delta = sizeof(uint32_t) * (j + repeats); - - reloc.presumed_offset = obj[1].offset; - offset = reloc.presumed_offset; - offset += reloc.delta; - - i = 16 * (j + repeats); - /* MI_STORE_REG_MEM */ - map[i++] = 0x24 << 23 | 1; - if (has_64bit_reloc) - map[i-1]++; - map[i++] = RCS_TIMESTAMP; /* ring local! */ - map[i++] = offset; - if (has_64bit_reloc) - map[i++] = offset >> 32; - map[i++] = MI_BATCH_BUFFER_END; - - gem_execbuf(fd, &execbuf); - } + for (j = 0; j < qlen; j++) { + execbuf.flags &= ~ENGINE_FLAGS; + execbuf.flags |= ring; + execbuf.batch_start_offset = 64 * j; + + gem_execbuf(fd, &execbuf); - if (flags & CORK) - igt_cork_unplug(&c); - gem_set_domain(fd, obj[1].handle, - I915_GEM_DOMAIN_GTT, - I915_GEM_DOMAIN_GTT); - igt_spin_batch_free(fd, spin); + execbuf.flags &= ~ENGINE_FLAGS; + execbuf.flags |= other; + execbuf.batch_start_offset = 64 * (j + qlen); - igt_info("%s-%s delay: %.2f\n", - name, e__->name, - (results[2*repeats-1] - results[0]) / (double)repeats); + gem_execbuf(fd, &execbuf); + } + + if (flags & CORK) + igt_cork_unplug(&c); + gem_set_domain(fd, obj[1].handle, + I915_GEM_DOMAIN_GTT, + I915_GEM_DOMAIN_GTT); + igt_spin_batch_free(fd, spin); + + igt_assert_eq_u64(obj[1].offset, + presumed_offset); + igt_stats_push(&stats, + ((uint64_t)(results[2*qlen-1] - results[0]) << 32) / qlen); + } + + igt_info("%s-%s-%d delay: %.2f\n", + name, e__->name, qlen, + igt_stats_get_median(&stats) / (1ull << 32)); + igt_stats_fini(&stats); + } } munmap(map, 64*1024); @@ -710,6 +690,11 @@ igt_main latency_from_ring(device, e->exec_id | e->flags, e->name, PREEMPT); + + igt_subtest_f("%s-preemption-queued", e->name) + latency_from_ring(device, + e->exec_id | e->flags, + e->name, PREEMPT | CORK); } } }