From patchwork Mon Jul 9 13:02:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 10514581 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D308B6032C for ; Mon, 9 Jul 2018 13:20:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BF6312894E for ; Mon, 9 Jul 2018 13:20:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B3D0028AFA; Mon, 9 Jul 2018 13:20:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A071F2894E for ; Mon, 9 Jul 2018 13:20:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 46B5388007; Mon, 9 Jul 2018 13:20:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id 90A8C6E45F for ; Mon, 9 Jul 2018 13:20:18 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 12296982-1500050 for multiple; Mon, 09 Jul 2018 14:02:05 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Mon, 9 Jul 2018 14:02:06 +0100 Message-Id: <20180709130208.11730-9-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180709130208.11730-1-chris@chris-wilson.co.uk> References: <20180709130208.11730-1-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 09/11] drm/i915: Dynamically allocate the array of drm_i915_gem_fence_reg X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP If we dynamically allocate the correct sized array for the fence registers, we can avoid the 4x overallocation on older, typically smaller devices and avoid having to know the static layout in advance. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 33 ------------ drivers/gpu/drm/i915/i915_gem_fence_reg.h | 2 - drivers/gpu/drm/i915/i915_gem_gtt.c | 64 +++++++++++++++++++++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 3 +- drivers/gpu/drm/i915/i915_vma.h | 1 + 5 files changed, 62 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 6a1bb88b5730..ca0400d30feb 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5628,39 +5628,6 @@ i915_gem_cleanup_engines(struct drm_i915_private *dev_priv) dev_priv->gt.cleanup_engine(engine); } -void i915_ggtt_init_fences(struct i915_ggtt *ggtt) -{ - struct drm_i915_private *dev_priv = ggtt->vm.i915; - int i; - - if (INTEL_GEN(dev_priv) >= 7 && !IS_VALLEYVIEW(dev_priv) && - !IS_CHERRYVIEW(dev_priv)) - ggtt->num_fence_regs = 32; - else if (INTEL_GEN(dev_priv) >= 4 || - IS_I945G(dev_priv) || IS_I945GM(dev_priv) || - IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) - ggtt->num_fence_regs = 16; - else - ggtt->num_fence_regs = 8; - - if (intel_vgpu_active(dev_priv)) - ggtt->num_fence_regs = I915_READ(vgtif_reg(avail_rs.fence_num)); - - INIT_LIST_HEAD(&ggtt->fence_list); - - /* Initialize fence registers to zero */ - for (i = 0; i < ggtt->num_fence_regs; i++) { - struct drm_i915_fence_reg *fence = &ggtt->fence_regs[i]; - - fence->ggtt = ggtt; - fence->id = i; - list_add_tail(&fence->link, &ggtt->fence_list); - } - i915_gem_restore_fences(dev_priv); - - i915_gem_detect_bit_6_swizzle(dev_priv); -} - static void i915_gem_init__mm(struct drm_i915_private *i915) { spin_lock_init(&i915->mm.object_stat_lock); diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.h b/drivers/gpu/drm/i915/i915_gem_fence_reg.h index c510f8efc1bb..6e66f6b3f851 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.h +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.h @@ -56,8 +56,6 @@ struct drm_i915_fence_reg { bool dirty; }; -void i915_ggtt_init_fences(struct i915_ggtt *ggtt); - struct drm_i915_fence_reg * i915_reserve_fence(struct drm_i915_private *i915); void i915_unreserve_fence(struct drm_i915_fence_reg *fence); diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index eda86afd7a45..06e779ed569f 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -37,6 +37,7 @@ #include #include "i915_drv.h" +#include "i915_gem_fence_reg.h" #include "i915_vgpu.h" #include "i915_trace.h" #include "intel_drv.h" @@ -2898,6 +2899,51 @@ void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915) ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma; } +static int i915_ggtt_init_fences(struct i915_ggtt *ggtt) +{ + struct drm_i915_private *dev_priv = ggtt->vm.i915; + int i; + + if (INTEL_GEN(dev_priv) >= 7 && + !(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) + ggtt->num_fence_regs = 32; + else if (INTEL_GEN(dev_priv) >= 4 || + IS_I945G(dev_priv) || IS_I945GM(dev_priv) || + IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) + ggtt->num_fence_regs = 16; + else + ggtt->num_fence_regs = 8; + + if (intel_vgpu_active(dev_priv)) + ggtt->num_fence_regs = I915_READ(vgtif_reg(avail_rs.fence_num)); + + ggtt->fence_regs = kcalloc(ggtt->num_fence_regs, + sizeof(*ggtt->fence_regs), + GFP_KERNEL); + if (!ggtt->fence_regs) + return -ENOMEM; + + INIT_LIST_HEAD(&ggtt->fence_list); + + /* Initialize fence registers to zero */ + for (i = 0; i < ggtt->num_fence_regs; i++) { + struct drm_i915_fence_reg *fence = &ggtt->fence_regs[i]; + + fence->ggtt = ggtt; + fence->id = i; + list_add_tail(&fence->link, &ggtt->fence_list); + } + i915_gem_restore_fences(dev_priv); + + i915_gem_detect_bit_6_swizzle(dev_priv); + return 0; +} + +static void i915_ggtt_cleanup_fences(struct i915_ggtt *ggtt) +{ + kfree(ggtt->fence_regs); +} + int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) { /* Let GEM Manage all of the aperture. @@ -2986,6 +3032,8 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) mutex_unlock(&dev_priv->drm.struct_mutex); + i915_ggtt_cleanup_fences(ggtt); + arch_phys_wc_del(ggtt->mtrr); io_mapping_fini(&ggtt->iomap); @@ -3591,13 +3639,15 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) ggtt->vm.mm.color_adjust = i915_gtt_color_adjust; mutex_unlock(&dev_priv->drm.struct_mutex); - i915_ggtt_init_fences(ggtt); + ret = i915_ggtt_init_fences(ggtt); + if (ret) + goto err_fini; if (!io_mapping_init_wc(&ggtt->iomap, ggtt->gmadr.start, ggtt->mappable_end)) { ret = -EIO; - goto out_gtt_cleanup; + goto err_fences; } ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end); @@ -3608,12 +3658,18 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) */ ret = i915_gem_init_stolen(dev_priv); if (ret) - goto out_gtt_cleanup; + goto err_io; return 0; -out_gtt_cleanup: +err_io: + arch_phys_wc_del(ggtt->mtrr); + io_mapping_fini(&ggtt->iomap); +err_fences: + i915_ggtt_cleanup_fences(ggtt); +err_fini: ggtt->vm.cleanup(&ggtt->vm); + i915_address_space_fini(&ggtt->vm); return ret; } diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 3d4c1b231420..6ef3f5377b3e 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -38,7 +38,6 @@ #include #include -#include "i915_gem_fence_reg.h" #include "i915_request.h" #include "i915_selftest.h" #include "i915_timeline.h" @@ -378,7 +377,7 @@ struct i915_ggtt { /** LRU list of objects with fence regs on them. */ struct list_head fence_list; - struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; + struct drm_i915_fence_reg *fence_regs; int num_fence_regs; struct drm_mm_node error_capture; diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index 925af79cc6d6..7df156e1ca06 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -30,6 +30,7 @@ #include +#include "i915_gem_fence_reg.h" #include "i915_gem_gtt.h" #include "i915_gem_object.h"