From patchwork Mon Jul 9 16:22:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 10515189 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7E03F60318 for ; Mon, 9 Jul 2018 16:22:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6A8AD28BD7 for ; Mon, 9 Jul 2018 16:22:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5B42128CA3; Mon, 9 Jul 2018 16:22:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C9F8C28BD7 for ; Mon, 9 Jul 2018 16:22:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F409A6E530; Mon, 9 Jul 2018 16:22:39 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id AF73A6E535 for ; Mon, 9 Jul 2018 16:22:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Jul 2018 09:22:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,330,1526367600"; d="scan'208";a="53079349" Received: from sgerwig-mobl1.amr.corp.intel.com (HELO ldmartin-desk.amr.corp.intel.com) ([10.254.26.234]) by fmsmga007.fm.intel.com with ESMTP; 09 Jul 2018 09:22:38 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Mon, 9 Jul 2018 09:22:22 -0700 Message-Id: <20180709162222.28125-2-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180709162222.28125-1-lucas.demarchi@intel.com> References: <20180709162222.28125-1-lucas.demarchi@intel.com> Subject: [Intel-gfx] [PATCH 2/2] drm/i915: remove PCH_GMBUS defines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rodrigo Vivi MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Now they are the same as GMBUS*, but without considering the different address bases. In order to use GMBUS* we just need access to dev_priv in a few places so this has been added. Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gvt/edid.c | 42 +++++++++++++++++------------ drivers/gpu/drm/i915/gvt/handlers.c | 8 +++--- drivers/gpu/drm/i915/i915_reg.h | 7 ----- 3 files changed, 29 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c index 4b98539025c5..3ffa814a634e 100644 --- a/drivers/gpu/drm/i915/gvt/edid.c +++ b/drivers/gpu/drm/i915/gvt/edid.c @@ -109,9 +109,11 @@ static inline int get_port_from_gmbus0(u32 gmbus0) static void reset_gmbus_controller(struct intel_vgpu *vgpu) { - vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY; + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; + + vgpu_vreg_t(vgpu, GMBUS2) = GMBUS_HW_RDY; if (!vgpu->display.i2c_edid.edid_available) - vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; + vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_SATOER; vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE; } @@ -141,22 +143,23 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu, vgpu->display.i2c_edid.state = I2C_GMBUS; vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE; - vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; - vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE; + vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_ACTIVE; + vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE; if (intel_vgpu_has_monitor_on_port(vgpu, port) && !intel_vgpu_port_is_dp(vgpu, port)) { vgpu->display.i2c_edid.port = port; vgpu->display.i2c_edid.edid_available = true; - vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER; + vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_SATOER; } else - vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; + vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_SATOER; return 0; } static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid; u32 slave_addr; u32 wvalue = *(u32 *)p_data; @@ -177,8 +180,8 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, * 2) HW_RDY bit asserted */ if (wvalue & GMBUS_SW_CLR_INT) { - vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT; - vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY; + vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_INT; + vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_HW_RDY; } /* For virtualization, we suppose that HW is always ready, @@ -226,7 +229,7 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, * visible in gmbus interface) */ i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE; - vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; + vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_ACTIVE; } break; case NIDX_NS_W: @@ -238,7 +241,7 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, * START (-->INDEX) -->DATA */ i2c_edid->gmbus.phase = GMBUS_DATA_PHASE; - vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE; + vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_ACTIVE; break; default: gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n"); @@ -265,6 +268,7 @@ static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; int i; unsigned char byte_data; struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid; @@ -274,7 +278,7 @@ static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, u32 reg_data = 0; /* Data can only be recevied if previous settings correct */ - if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) { + if (vgpu_vreg_t(vgpu, GMBUS1) & GMBUS_SLAVE_READ) { if (byte_left <= 0) { memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); return 0; @@ -350,12 +354,14 @@ static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; + if (WARN_ON(bytes > 8 && (offset & (bytes - 1)))) return -EINVAL; - if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) + if (offset == i915_mmio_reg_offset(GMBUS2)) return gmbus2_mmio_read(vgpu, offset, p_data, bytes); - else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) + else if (offset == i915_mmio_reg_offset(GMBUS3)) return gmbus3_mmio_read(vgpu, offset, p_data, bytes); memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); @@ -375,16 +381,18 @@ int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu, int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; + if (WARN_ON(bytes > 8 && (offset & (bytes - 1)))) return -EINVAL; - if (offset == i915_mmio_reg_offset(PCH_GMBUS0)) + if (offset == i915_mmio_reg_offset(GMBUS0)) return gmbus0_mmio_write(vgpu, offset, p_data, bytes); - else if (offset == i915_mmio_reg_offset(PCH_GMBUS1)) + else if (offset == i915_mmio_reg_offset(GMBUS1)) return gmbus1_mmio_write(vgpu, offset, p_data, bytes); - else if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) + else if (offset == i915_mmio_reg_offset(GMBUS2)) return gmbus2_mmio_write(vgpu, offset, p_data, bytes); - else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) + else if (offset == i915_mmio_reg_offset(GMBUS3)) return gmbus3_mmio_write(vgpu, offset, p_data, bytes); memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index e25a74fe753b..6ead029dbb48 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -2082,8 +2082,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_D(_MMIO(0x48268), D_ALL); - MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, - gmbus_mmio_write); + MMIO_F(GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, + gmbus_mmio_write); MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); @@ -2473,8 +2473,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_D(_MMIO(0xe6704), D_ALL); MMIO_D(_MMIO(0xe6800), D_ALL); MMIO_D(_MMIO(0xe6804), D_ALL); - MMIO_D(PCH_GMBUS4, D_ALL); - MMIO_D(PCH_GMBUS5, D_ALL); + MMIO_D(GMBUS4, D_ALL); + MMIO_D(GMBUS5, D_ALL); MMIO_D(_MMIO(0x902c), D_ALL); MMIO_D(_MMIO(0xec008), D_ALL); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f8f71d577613..0baafabcf52c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7678,13 +7678,6 @@ enum { #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4) #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) -#define PCH_GMBUS0 _MMIO(0xc5100) -#define PCH_GMBUS1 _MMIO(0xc5104) -#define PCH_GMBUS2 _MMIO(0xc5108) -#define PCH_GMBUS3 _MMIO(0xc510c) -#define PCH_GMBUS4 _MMIO(0xc5110) -#define PCH_GMBUS5 _MMIO(0xc5120) - #define _PCH_DPLL_A 0xc6014 #define _PCH_DPLL_B 0xc6018 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)