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[17/18] drm/i915: Bump gen4+ fb stride limit to 256KiB

Message ID 20180719182214.4323-18-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä July 19, 2018, 6:22 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

With gtt remapping plugged in we can simply raise the stride
limit on gen4+. Let's just arbitraily pick 256 KiB as the limit.

No remapping CCS because the virtual address of each page actually
matters due to the new hash mode
(WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no remapping
on gen2/3 due to lack of fence on the remapped vma.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Souza, Jose Aug. 24, 2018, 8:49 p.m. UTC | #1 
On Thu, 2018-07-19 at 21:22 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> With gtt remapping plugged in we can simply raise the stride
> limit on gen4+. Let's just arbitraily pick 256 KiB as the limit.
> 
> No remapping CCS because the virtual address of each page actually
> matters due to the new hash mode
> (WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no
> remapping
> on gen2/3 due to lack of fence on the remapped vma.

With someone else review in patch 15 and 16:

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>


> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 8fb78214b4be..fa199f469e81 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2505,6 +2505,19 @@ static
>  u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
>  			u32 pixel_format, u64 modifier)
>  {
> +	/*
> +	 * Arbitrary limit for gen4+. We can deal with any page
> +	 * aligned stride via GTT remapping. Gen2/3 need a fence
> +	 * for tiled scanout which the remapped vma won't have,
> +	 * so we don't allow remapping on those platforms.
> +	 *
> +	 * Also the new hash mode we use for CCS isn't compatible
> +	 * with remapping as the virtual address of the pages
> +	 * affects the compressed data.
> +	 */
> +	if (INTEL_GEN(dev_priv) >= 4 &&
> !intel_modifier_has_ccs(modifier))
> +		return 256*1024;
> +
>  	return intel_plane_fb_max_stride(dev_priv, pixel_format,
> modifier);
>  }
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8fb78214b4be..fa199f469e81 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2505,6 +2505,19 @@  static
 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
 			u32 pixel_format, u64 modifier)
 {
+	/*
+	 * Arbitrary limit for gen4+. We can deal with any page
+	 * aligned stride via GTT remapping. Gen2/3 need a fence
+	 * for tiled scanout which the remapped vma won't have,
+	 * so we don't allow remapping on those platforms.
+	 *
+	 * Also the new hash mode we use for CCS isn't compatible
+	 * with remapping as the virtual address of the pages
+	 * affects the compressed data.
+	 */
+	if (INTEL_GEN(dev_priv) >= 4 && !intel_modifier_has_ccs(modifier))
+		return 256*1024;
+
 	return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
 }