| Message ID | 20180720141504.22832-6-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Em Sex, 2018-07-20 às 17:14 +0300, Imre Deak escreveu: > Atm, we determine the control/status flag offsets within the PUNIT > control/status registers based on the power well's ID. Since the > power > well ID enum is global across all platforms, the associated macros to > get the flag offsets involves some magic. This makes checking the > register/bit definitions against the specification more difficult > than > necessary. Also the values in the power well ID enum must stay fixed, > making code maintenance of the enum cumbersome. > > To solve the above define the control/status flag indices right after > the corresponding registers and use these to derive the > control/status > flag values by storing the indices in the i915_power_well_desc > struct. > > Initializing anonymous unions requires - even named - initializers to > be in order of the struct declaration, hence the reordering of the > .id > fields. My C-fu is not as strong as I thought it was. After some playing with this it seems the only requirement is to initialize the enum exactly after .id. Ok. But then, since we're reordering anyway, shouldn't we also move .ops down when relevant, and keep the ordering "perfect" for every member? Anyway, the patch does what it says, so with or without the new color: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Cc: Jani Nikula <jani.nikula@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 7 +++++ > drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++---- > drivers/gpu/drm/i915/intel_runtime_pm.c | 52 > ++++++++++++++++++++++++--------- > 3 files changed, 62 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > b/drivers/gpu/drm/i915/i915_drv.h > index 3ae200a9e8f1..d31a8ef05d18 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -874,6 +874,13 @@ struct i915_power_well_desc { > */ > union { > struct { > + /* > + * request/status flag index in the PUNIT > power well > + * control/status registers. > + */ > + u8 idx; > + } vlv; > + struct { > enum dpio_phy phy; > } bxt; > struct { > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index 8af945d8a995..f76bb4f3c944 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1144,11 +1144,23 @@ enum i915_power_well_id { > > #define PUNIT_REG_PWRGT_CTRL 0x60 > #define PUNIT_REG_PWRGT_STATUS 0x61 > -#define PUNIT_PWRGT_MASK(power_well) (3 << > ((power_well) * 2)) > -#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) > * 2)) > -#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << > ((power_well) * 2)) > -#define PUNIT_PWRGT_RESET(power_well) (2 << > ((power_well) * 2)) > -#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << > ((power_well) * 2)) > +#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * > 2)) > +#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) > * 2)) > +#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << > ((pw_idx) * 2)) > +#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * > 2)) > +#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << > ((pw_idx) * 2)) > + > +#define PUNIT_PWGT_IDX_RENDER 0 > +#define PUNIT_PWGT_IDX_MEDIA 1 > +#define PUNIT_PWGT_IDX_DISP2D 3 > +#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5 > +#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6 > +#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7 > +#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8 > +#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9 > +#define PUNIT_PWGT_IDX_DPIO_RX0 10 > +#define PUNIT_PWGT_IDX_DPIO_RX1 11 > +#define PUNIT_PWGT_IDX_DPIO_CMN_D 12 > > #define PUNIT_REG_GPU_LFM 0xd3 > #define PUNIT_REG_GPU_FREQ_REQ 0xd4 > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c > b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 8b3c241bee55..05d8cdab08cc 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -872,14 +872,14 @@ static void > i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, > static void vlv_set_power_well(struct drm_i915_private *dev_priv, > struct i915_power_well *power_well, > bool enable) > { > - enum i915_power_well_id power_well_id = power_well->desc- > >id; > + int pw_idx = power_well->desc->vlv.idx; > u32 mask; > u32 state; > u32 ctrl; > > - mask = PUNIT_PWRGT_MASK(power_well_id); > - state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : > - PUNIT_PWRGT_PWR_GATE(power_well_id); > + mask = PUNIT_PWRGT_MASK(pw_idx); > + state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : > + PUNIT_PWRGT_PWR_GATE(pw_idx); > > mutex_lock(&dev_priv->pcu_lock); > > @@ -920,14 +920,14 @@ static void vlv_power_well_disable(struct > drm_i915_private *dev_priv, > static bool vlv_power_well_enabled(struct drm_i915_private > *dev_priv, > struct i915_power_well > *power_well) > { > - enum i915_power_well_id power_well_id = power_well->desc- > >id; > + int pw_idx = power_well->desc->vlv.idx; > bool enabled = false; > u32 mask; > u32 state; > u32 ctrl; > > - mask = PUNIT_PWRGT_MASK(power_well_id); > - ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); > + mask = PUNIT_PWRGT_MASK(pw_idx); > + ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); > > mutex_lock(&dev_priv->pcu_lock); > > @@ -936,8 +936,8 @@ static bool vlv_power_well_enabled(struct > drm_i915_private *dev_priv, > * We only ever set the power-on and power-gate states, > anything > * else is unexpected. > */ > - WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && > - state != PUNIT_PWRGT_PWR_GATE(power_well_id)); > + WARN_ON(state != PUNIT_PWRGT_PWR_ON(pw_idx) && > + state != PUNIT_PWRGT_PWR_GATE(pw_idx)); > if (state == ctrl) > enabled = true; > > @@ -2179,8 +2179,11 @@ static const struct i915_power_well_desc > vlv_power_wells[] = { > { > .name = "display", > .domains = VLV_DISPLAY_POWER_DOMAINS, > - .id = PUNIT_POWER_WELL_DISP2D, > .ops = &vlv_display_power_well_ops, > + .id = PUNIT_POWER_WELL_DISP2D, > + { > + .vlv.idx = PUNIT_PWGT_IDX_DISP2D, > + }, > }, > { > .name = "dpio-tx-b-01", > @@ -2190,6 +2193,9 @@ static const struct i915_power_well_desc > vlv_power_wells[] = { > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > .ops = &vlv_dpio_power_well_ops, > .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, > + { > + .vlv.idx = > PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01, > + }, > }, > { > .name = "dpio-tx-b-23", > @@ -2199,6 +2205,9 @@ static const struct i915_power_well_desc > vlv_power_wells[] = { > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > .ops = &vlv_dpio_power_well_ops, > .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, > + { > + .vlv.idx = > PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23, > + }, > }, > { > .name = "dpio-tx-c-01", > @@ -2208,6 +2217,9 @@ static const struct i915_power_well_desc > vlv_power_wells[] = { > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > .ops = &vlv_dpio_power_well_ops, > .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, > + { > + .vlv.idx = > PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01, > + }, > }, > { > .name = "dpio-tx-c-23", > @@ -2217,12 +2229,18 @@ static const struct i915_power_well_desc > vlv_power_wells[] = { > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > .ops = &vlv_dpio_power_well_ops, > .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, > + { > + .vlv.idx = > PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23, > + }, > }, > { > .name = "dpio-common", > .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, > - .id = PUNIT_POWER_WELL_DPIO_CMN_BC, > .ops = &vlv_dpio_cmn_power_well_ops, > + .id = PUNIT_POWER_WELL_DPIO_CMN_BC, > + { > + .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, > + }, > }, > }; > > @@ -2242,20 +2260,26 @@ static const struct i915_power_well_desc > chv_power_wells[] = { > * required for any pipe to work. > */ > .domains = CHV_DISPLAY_POWER_DOMAINS, > - .id = CHV_DISP_PW_PIPE_A, > .ops = &chv_pipe_power_well_ops, > + .id = CHV_DISP_PW_PIPE_A, > }, > { > .name = "dpio-common-bc", > .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, > - .id = PUNIT_POWER_WELL_DPIO_CMN_BC, > .ops = &chv_dpio_cmn_power_well_ops, > + .id = PUNIT_POWER_WELL_DPIO_CMN_BC, > + { > + .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, > + }, > }, > { > .name = "dpio-common-d", > .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, > + .ops = &chv_dpio_cmn_power_well_ops, > .id = PUNIT_POWER_WELL_DPIO_CMN_D, > - .ops = &chv_dpio_cmn_power_well_ops, > + { > + .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D, > + }, > }, > }; >
On Wed, Aug 01, 2018 at 03:15:40PM -0700, Paulo Zanoni wrote: > Em Sex, 2018-07-20 às 17:14 +0300, Imre Deak escreveu: > > Atm, we determine the control/status flag offsets within the PUNIT > > control/status registers based on the power well's ID. Since the > > power > > well ID enum is global across all platforms, the associated macros to > > get the flag offsets involves some magic. This makes checking the > > register/bit definitions against the specification more difficult > > than > > necessary. Also the values in the power well ID enum must stay fixed, > > making code maintenance of the enum cumbersome. > > > > To solve the above define the control/status flag indices right after > > the corresponding registers and use these to derive the > > control/status > > flag values by storing the indices in the i915_power_well_desc > > struct. > > > > Initializing anonymous unions requires - even named - initializers to > > be in order of the struct declaration, hence the reordering of the > > .id > > fields. > > My C-fu is not as strong as I thought it was. After some playing with > this it seems the only requirement is to initialize the enum exactly > after .id. Ok. Hm, right the only requirement is that the field right before the anonymous initializer is explicitly intialized and it's initialized in the order the fields are listed in the struct declaration. The init order of the other fields don't seem to play a role in this. I'll correct this in the commit message. > > But then, since we're reordering anyway, shouldn't we also move .ops > down when relevant, and keep the ordering "perfect" for every member? My thinking was to keep the fields in the initializers in the beginning that need to be provided for all power wells, while keep the anonymous union initializer at the end since it's either power well specific, or doesn't need to be provided at all. So, we could consider to move .ops accordingly in the struct declaration earlier, even saving some space due to alignment. Will think about it as a follow-up. > > Anyway, the patch does what it says, so with or without the new color: > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > > > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Cc: Jani Nikula <jani.nikula@intel.com> > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > --- > > drivers/gpu/drm/i915/i915_drv.h | 7 +++++ > > drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++---- > > drivers/gpu/drm/i915/intel_runtime_pm.c | 52 > > ++++++++++++++++++++++++--------- > > 3 files changed, 62 insertions(+), 19 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > > b/drivers/gpu/drm/i915/i915_drv.h > > index 3ae200a9e8f1..d31a8ef05d18 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -874,6 +874,13 @@ struct i915_power_well_desc { > > */ > > union { > > struct { > > + /* > > + * request/status flag index in the PUNIT > > power well > > + * control/status registers. > > + */ > > + u8 idx; > > + } vlv; > > + struct { > > enum dpio_phy phy; > > } bxt; > > struct { > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index 8af945d8a995..f76bb4f3c944 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1144,11 +1144,23 @@ enum i915_power_well_id { > > > > #define PUNIT_REG_PWRGT_CTRL 0x60 > > #define PUNIT_REG_PWRGT_STATUS 0x61 > > -#define PUNIT_PWRGT_MASK(power_well) (3 << > > ((power_well) * 2)) > > -#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) > > * 2)) > > -#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << > > ((power_well) * 2)) > > -#define PUNIT_PWRGT_RESET(power_well) (2 << > > ((power_well) * 2)) > > -#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << > > ((power_well) * 2)) > > +#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * > > 2)) > > +#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) > > * 2)) > > +#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << > > ((pw_idx) * 2)) > > +#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * > > 2)) > > +#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << > > ((pw_idx) * 2)) > > + > > +#define PUNIT_PWGT_IDX_RENDER 0 > > +#define PUNIT_PWGT_IDX_MEDIA 1 > > +#define PUNIT_PWGT_IDX_DISP2D 3 > > +#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5 > > +#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6 > > +#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7 > > +#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8 > > +#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9 > > +#define PUNIT_PWGT_IDX_DPIO_RX0 10 > > +#define PUNIT_PWGT_IDX_DPIO_RX1 11 > > +#define PUNIT_PWGT_IDX_DPIO_CMN_D 12 > > > > #define PUNIT_REG_GPU_LFM 0xd3 > > #define PUNIT_REG_GPU_FREQ_REQ 0xd4 > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c > > b/drivers/gpu/drm/i915/intel_runtime_pm.c > > index 8b3c241bee55..05d8cdab08cc 100644 > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > > @@ -872,14 +872,14 @@ static void > > i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, > > static void vlv_set_power_well(struct drm_i915_private *dev_priv, > > struct i915_power_well *power_well, > > bool enable) > > { > > - enum i915_power_well_id power_well_id = power_well->desc- > > >id; > > + int pw_idx = power_well->desc->vlv.idx; > > u32 mask; > > u32 state; > > u32 ctrl; > > > > - mask = PUNIT_PWRGT_MASK(power_well_id); > > - state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : > > - PUNIT_PWRGT_PWR_GATE(power_well_id); > > + mask = PUNIT_PWRGT_MASK(pw_idx); > > + state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : > > + PUNIT_PWRGT_PWR_GATE(pw_idx); > > > > mutex_lock(&dev_priv->pcu_lock); > > > > @@ -920,14 +920,14 @@ static void vlv_power_well_disable(struct > > drm_i915_private *dev_priv, > > static bool vlv_power_well_enabled(struct drm_i915_private > > *dev_priv, > > struct i915_power_well > > *power_well) > > { > > - enum i915_power_well_id power_well_id = power_well->desc- > > >id; > > + int pw_idx = power_well->desc->vlv.idx; > > bool enabled = false; > > u32 mask; > > u32 state; > > u32 ctrl; > > > > - mask = PUNIT_PWRGT_MASK(power_well_id); > > - ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); > > + mask = PUNIT_PWRGT_MASK(pw_idx); > > + ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); > > > > mutex_lock(&dev_priv->pcu_lock); > > > > @@ -936,8 +936,8 @@ static bool vlv_power_well_enabled(struct > > drm_i915_private *dev_priv, > > * We only ever set the power-on and power-gate states, > > anything > > * else is unexpected. > > */ > > - WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && > > - state != PUNIT_PWRGT_PWR_GATE(power_well_id)); > > + WARN_ON(state != PUNIT_PWRGT_PWR_ON(pw_idx) && > > + state != PUNIT_PWRGT_PWR_GATE(pw_idx)); > > if (state == ctrl) > > enabled = true; > > > > @@ -2179,8 +2179,11 @@ static const struct i915_power_well_desc > > vlv_power_wells[] = { > > { > > .name = "display", > > .domains = VLV_DISPLAY_POWER_DOMAINS, > > - .id = PUNIT_POWER_WELL_DISP2D, > > .ops = &vlv_display_power_well_ops, > > + .id = PUNIT_POWER_WELL_DISP2D, > > + { > > + .vlv.idx = PUNIT_PWGT_IDX_DISP2D, > > + }, > > }, > > { > > .name = "dpio-tx-b-01", > > @@ -2190,6 +2193,9 @@ static const struct i915_power_well_desc > > vlv_power_wells[] = { > > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > > .ops = &vlv_dpio_power_well_ops, > > .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, > > + { > > + .vlv.idx = > > PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01, > > + }, > > }, > > { > > .name = "dpio-tx-b-23", > > @@ -2199,6 +2205,9 @@ static const struct i915_power_well_desc > > vlv_power_wells[] = { > > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > > .ops = &vlv_dpio_power_well_ops, > > .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, > > + { > > + .vlv.idx = > > PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23, > > + }, > > }, > > { > > .name = "dpio-tx-c-01", > > @@ -2208,6 +2217,9 @@ static const struct i915_power_well_desc > > vlv_power_wells[] = { > > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > > .ops = &vlv_dpio_power_well_ops, > > .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, > > + { > > + .vlv.idx = > > PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01, > > + }, > > }, > > { > > .name = "dpio-tx-c-23", > > @@ -2217,12 +2229,18 @@ static const struct i915_power_well_desc > > vlv_power_wells[] = { > > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > > .ops = &vlv_dpio_power_well_ops, > > .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, > > + { > > + .vlv.idx = > > PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23, > > + }, > > }, > > { > > .name = "dpio-common", > > .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, > > - .id = PUNIT_POWER_WELL_DPIO_CMN_BC, > > .ops = &vlv_dpio_cmn_power_well_ops, > > + .id = PUNIT_POWER_WELL_DPIO_CMN_BC, > > + { > > + .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, > > + }, > > }, > > }; > > > > @@ -2242,20 +2260,26 @@ static const struct i915_power_well_desc > > chv_power_wells[] = { > > * required for any pipe to work. > > */ > > .domains = CHV_DISPLAY_POWER_DOMAINS, > > - .id = CHV_DISP_PW_PIPE_A, > > .ops = &chv_pipe_power_well_ops, > > + .id = CHV_DISP_PW_PIPE_A, > > }, > > { > > .name = "dpio-common-bc", > > .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, > > - .id = PUNIT_POWER_WELL_DPIO_CMN_BC, > > .ops = &chv_dpio_cmn_power_well_ops, > > + .id = PUNIT_POWER_WELL_DPIO_CMN_BC, > > + { > > + .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, > > + }, > > }, > > { > > .name = "dpio-common-d", > > .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, > > + .ops = &chv_dpio_cmn_power_well_ops, > > .id = PUNIT_POWER_WELL_DPIO_CMN_D, > > - .ops = &chv_dpio_cmn_power_well_ops, > > + { > > + .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D, > > + }, > > }, > > }; > >
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3ae200a9e8f1..d31a8ef05d18 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -874,6 +874,13 @@ struct i915_power_well_desc { */ union { struct { + /* + * request/status flag index in the PUNIT power well + * control/status registers. + */ + u8 idx; + } vlv; + struct { enum dpio_phy phy; } bxt; struct { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8af945d8a995..f76bb4f3c944 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1144,11 +1144,23 @@ enum i915_power_well_id { #define PUNIT_REG_PWRGT_CTRL 0x60 #define PUNIT_REG_PWRGT_STATUS 0x61 -#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) -#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) -#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) -#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) -#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) +#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2)) +#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2)) +#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2)) +#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2)) +#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2)) + +#define PUNIT_PWGT_IDX_RENDER 0 +#define PUNIT_PWGT_IDX_MEDIA 1 +#define PUNIT_PWGT_IDX_DISP2D 3 +#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5 +#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6 +#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7 +#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8 +#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9 +#define PUNIT_PWGT_IDX_DPIO_RX0 10 +#define PUNIT_PWGT_IDX_DPIO_RX1 11 +#define PUNIT_PWGT_IDX_DPIO_CMN_D 12 #define PUNIT_REG_GPU_LFM 0xd3 #define PUNIT_REG_GPU_FREQ_REQ 0xd4 diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 8b3c241bee55..05d8cdab08cc 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -872,14 +872,14 @@ static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, static void vlv_set_power_well(struct drm_i915_private *dev_priv, struct i915_power_well *power_well, bool enable) { - enum i915_power_well_id power_well_id = power_well->desc->id; + int pw_idx = power_well->desc->vlv.idx; u32 mask; u32 state; u32 ctrl; - mask = PUNIT_PWRGT_MASK(power_well_id); - state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : - PUNIT_PWRGT_PWR_GATE(power_well_id); + mask = PUNIT_PWRGT_MASK(pw_idx); + state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : + PUNIT_PWRGT_PWR_GATE(pw_idx); mutex_lock(&dev_priv->pcu_lock); @@ -920,14 +920,14 @@ static void vlv_power_well_disable(struct drm_i915_private *dev_priv, static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - enum i915_power_well_id power_well_id = power_well->desc->id; + int pw_idx = power_well->desc->vlv.idx; bool enabled = false; u32 mask; u32 state; u32 ctrl; - mask = PUNIT_PWRGT_MASK(power_well_id); - ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); + mask = PUNIT_PWRGT_MASK(pw_idx); + ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); mutex_lock(&dev_priv->pcu_lock); @@ -936,8 +936,8 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, * We only ever set the power-on and power-gate states, anything * else is unexpected. */ - WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && - state != PUNIT_PWRGT_PWR_GATE(power_well_id)); + WARN_ON(state != PUNIT_PWRGT_PWR_ON(pw_idx) && + state != PUNIT_PWRGT_PWR_GATE(pw_idx)); if (state == ctrl) enabled = true; @@ -2179,8 +2179,11 @@ static const struct i915_power_well_desc vlv_power_wells[] = { { .name = "display", .domains = VLV_DISPLAY_POWER_DOMAINS, - .id = PUNIT_POWER_WELL_DISP2D, .ops = &vlv_display_power_well_ops, + .id = PUNIT_POWER_WELL_DISP2D, + { + .vlv.idx = PUNIT_PWGT_IDX_DISP2D, + }, }, { .name = "dpio-tx-b-01", @@ -2190,6 +2193,9 @@ static const struct i915_power_well_desc vlv_power_wells[] = { VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, .ops = &vlv_dpio_power_well_ops, .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, + { + .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01, + }, }, { .name = "dpio-tx-b-23", @@ -2199,6 +2205,9 @@ static const struct i915_power_well_desc vlv_power_wells[] = { VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, .ops = &vlv_dpio_power_well_ops, .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, + { + .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23, + }, }, { .name = "dpio-tx-c-01", @@ -2208,6 +2217,9 @@ static const struct i915_power_well_desc vlv_power_wells[] = { VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, .ops = &vlv_dpio_power_well_ops, .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, + { + .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01, + }, }, { .name = "dpio-tx-c-23", @@ -2217,12 +2229,18 @@ static const struct i915_power_well_desc vlv_power_wells[] = { VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, .ops = &vlv_dpio_power_well_ops, .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, + { + .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23, + }, }, { .name = "dpio-common", .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, - .id = PUNIT_POWER_WELL_DPIO_CMN_BC, .ops = &vlv_dpio_cmn_power_well_ops, + .id = PUNIT_POWER_WELL_DPIO_CMN_BC, + { + .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, + }, }, }; @@ -2242,20 +2260,26 @@ static const struct i915_power_well_desc chv_power_wells[] = { * required for any pipe to work. */ .domains = CHV_DISPLAY_POWER_DOMAINS, - .id = CHV_DISP_PW_PIPE_A, .ops = &chv_pipe_power_well_ops, + .id = CHV_DISP_PW_PIPE_A, }, { .name = "dpio-common-bc", .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, - .id = PUNIT_POWER_WELL_DPIO_CMN_BC, .ops = &chv_dpio_cmn_power_well_ops, + .id = PUNIT_POWER_WELL_DPIO_CMN_BC, + { + .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, + }, }, { .name = "dpio-common-d", .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, + .ops = &chv_dpio_cmn_power_well_ops, .id = PUNIT_POWER_WELL_DPIO_CMN_D, - .ops = &chv_dpio_cmn_power_well_ops, + { + .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D, + }, }, };
Atm, we determine the control/status flag offsets within the PUNIT control/status registers based on the power well's ID. Since the power well ID enum is global across all platforms, the associated macros to get the flag offsets involves some magic. This makes checking the register/bit definitions against the specification more difficult than necessary. Also the values in the power well ID enum must stay fixed, making code maintenance of the enum cumbersome. To solve the above define the control/status flag indices right after the corresponding registers and use these to derive the control/status flag values by storing the indices in the i915_power_well_desc struct. Initializing anonymous unions requires - even named - initializers to be in order of the struct declaration, hence the reordering of the .id fields. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 7 +++++ drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++---- drivers/gpu/drm/i915/intel_runtime_pm.c | 52 ++++++++++++++++++++++++--------- 3 files changed, 62 insertions(+), 19 deletions(-)