| Message ID | 20180720141504.22832-8-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Em Sex, 2018-07-20 às 17:15 +0300, Imre Deak escreveu: > Now that we removed dependence on the power well IDs to determine the > control register and request/status flag offsets the only purpose of > power well IDs is to look up power wells directly bypassing the power > domains framework. However this direct lookup isn't needed for most > of > the exisiting power wells and hopefully won't be needed for any new > power wells in the future. To make maintenance of the power well ID > enum > easier, don't require a unique ID for each power well, only if it's > necessary. Remove the IDs becoming redundant this way and assign to > all > the corresponding power wells a new DISP_PW_ID_NONE ID. > > After the previous two patches the IDs don't need to have a fixed > value, > so remove the explicit initializers and adjust the enum's code > comment > accordingly. I would probably have kept every enum, but let's proceed with your colors. More below: > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Cc: Jani Nikula <jani.nikula@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 118 ++++---------------- > --------- > drivers/gpu/drm/i915/intel_runtime_pm.c | 129 ++++++++++++++++---- > ------------ > 2 files changed, 79 insertions(+), 168 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index b7022fb8d524..9b3635009826 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1029,117 +1029,25 @@ static inline bool > i915_mmio_reg_valid(i915_reg_t reg) > /* > * i915_power_well_id: > * > - * Platform specific IDs used to look up power wells and - except > for custom > - * power wells - to define request/status register flag bit > positions. As such > - * the set of IDs on a given platform must be unique and except for > custom > - * power wells their value must stay fixed. > + * IDs used to look up power wells. Power wells accessed directly > bypassing > + * the power domains framework must be assigned a unique ID. The > rest of power > + * wells must be assigned DISP_PW_ID_NONE. > */ > enum i915_power_well_id { > - /* > - * I830 > - * - custom power well > - */ > - I830_DISP_PW_PIPES = 0, > - > - /* > - * VLV/CHV > - * - PUNIT_REG_PWRGT_CTRL (bit: id*2), > - * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8) > - */ > - PUNIT_POWER_WELL_RENDER = 0, > - PUNIT_POWER_WELL_MEDIA = 1, > - PUNIT_POWER_WELL_DISP2D = 3, > - PUNIT_POWER_WELL_DPIO_CMN_BC = 5, > - PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, > - PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, > - PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, > - PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, > - PUNIT_POWER_WELL_DPIO_RX0 = 10, > - PUNIT_POWER_WELL_DPIO_RX1 = 11, > - PUNIT_POWER_WELL_DPIO_CMN_D = 12, > - /* - custom power well */ > - CHV_DISP_PW_PIPE_A, /* 13 */ > - > - /* > - * HSW/BDW > - * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: > id*2+1) > - */ > - HSW_DISP_PW_GLOBAL = 15, > - > - /* > - * GEN9+ > - * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: > id*2+1) > - */ > - SKL_DISP_PW_MISC_IO = 0, > - SKL_DISP_PW_DDI_A_E, > - GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, > - CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, > - SKL_DISP_PW_DDI_B, > - SKL_DISP_PW_DDI_C, > - SKL_DISP_PW_DDI_D, > - CNL_DISP_PW_DDI_F = 6, > - > - GLK_DISP_PW_AUX_A = 8, > - GLK_DISP_PW_AUX_B, > - GLK_DISP_PW_AUX_C, > - CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A, > - CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B, > - CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C, > - CNL_DISP_PW_AUX_D, > - CNL_DISP_PW_AUX_F, > - > - SKL_DISP_PW_1 = 14, > + DISP_PW_ID_NONE, > + > + PUNIT_POWER_WELL_DISP2D, > + PUNIT_POWER_WELL_DPIO_CMN_BC, > + PUNIT_POWER_WELL_DPIO_CMN_D, > + HSW_DISP_PW_GLOBAL, Looking up this one (from intel_hdcp.c) will fail to find any power wells because they got changed to DISP_PW_ID_NONE. > + SKL_DISP_PW_MISC_IO, > + SKL_DISP_PW_1, > SKL_DISP_PW_2, > - > - /* - custom power wells */ > BXT_DPIO_CMN_A, > BXT_DPIO_CMN_BC, > - GLK_DPIO_CMN_C, /* 18 */ > - > - /* > - * GEN11+ > - * - _HSW_PWR_WELL_CTL1-4 > - * (status bit: (id&15)*2, req bit:(id&15)*2+1) > - */ > - ICL_DISP_PW_1 = 0, > + GLK_DPIO_CMN_C, > + ICL_DISP_PW_1, > ICL_DISP_PW_2, Either we kill ICL_DISP_PW_2 or we don't switch its power wells to DISP_PW_ID_NONE. I suppose killing ICL_DISP_PW_2 is the direction we're moving to. > - ICL_DISP_PW_3, > - ICL_DISP_PW_4, > - > - /* > - * - _HSW_PWR_WELL_CTL_AUX1/2/4 > - * (status bit: (id&15)*2, req bit:(id&15)*2+1) > - */ > - ICL_DISP_PW_AUX_A = 16, > - ICL_DISP_PW_AUX_B, > - ICL_DISP_PW_AUX_C, > - ICL_DISP_PW_AUX_D, > - ICL_DISP_PW_AUX_E, > - ICL_DISP_PW_AUX_F, > - > - ICL_DISP_PW_AUX_TBT1 = 24, > - ICL_DISP_PW_AUX_TBT2, > - ICL_DISP_PW_AUX_TBT3, > - ICL_DISP_PW_AUX_TBT4, > - > - /* > - * - _HSW_PWR_WELL_CTL_DDI1/2/4 > - * (status bit: (id&15)*2, req bit:(id&15)*2+1) > - */ > - ICL_DISP_PW_DDI_A = 32, > - ICL_DISP_PW_DDI_B, > - ICL_DISP_PW_DDI_C, > - ICL_DISP_PW_DDI_D, > - ICL_DISP_PW_DDI_E, > - ICL_DISP_PW_DDI_F, /* 37 */ > - > - /* > - * Multiple platforms. > - * Must start following the highest ID of any platform. > - * - custom power wells > - */ > - SKL_DISP_PW_DC_OFF = 38, > - I915_DISP_PW_ALWAYS_ON, > }; > > #define PUNIT_REG_PWRGT_CTRL 0x60 > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c > b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 5527504d664f..792394d20f62 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -2067,7 +2067,7 @@ static const struct i915_power_well_desc > i9xx_always_on_power_well[] = { > .always_on = 1, > .domains = POWER_DOMAIN_MASK, > .ops = &i9xx_always_on_power_well_ops, > - .id = I915_DISP_PW_ALWAYS_ON, > + .id = DISP_PW_ID_NONE, > }, > }; > > @@ -2084,13 +2084,13 @@ static const struct i915_power_well_desc > i830_power_wells[] = { > .always_on = 1, > .domains = POWER_DOMAIN_MASK, > .ops = &i9xx_always_on_power_well_ops, > - .id = I915_DISP_PW_ALWAYS_ON, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "pipes", > .domains = I830_PIPES_POWER_DOMAINS, > .ops = &i830_pipes_power_well_ops, > - .id = I830_DISP_PW_PIPES, > + .id = DISP_PW_ID_NONE, > }, > }; > > @@ -2128,13 +2128,13 @@ static const struct i915_power_well_desc > hsw_power_wells[] = { > .always_on = 1, > .domains = POWER_DOMAIN_MASK, > .ops = &i9xx_always_on_power_well_ops, > - .id = I915_DISP_PW_ALWAYS_ON, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "display", > .domains = HSW_DISPLAY_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = HSW_DISP_PW_GLOBAL, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, > @@ -2149,13 +2149,13 @@ static const struct i915_power_well_desc > bdw_power_wells[] = { > .always_on = 1, > .domains = POWER_DOMAIN_MASK, > .ops = &i9xx_always_on_power_well_ops, > - .id = I915_DISP_PW_ALWAYS_ON, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "display", > .domains = BDW_DISPLAY_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = HSW_DISP_PW_GLOBAL, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, > @@ -2192,7 +2192,7 @@ static const struct i915_power_well_desc > vlv_power_wells[] = { > .always_on = 1, > .domains = POWER_DOMAIN_MASK, > .ops = &i9xx_always_on_power_well_ops, > - .id = I915_DISP_PW_ALWAYS_ON, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "display", > @@ -2210,7 +2210,7 @@ static const struct i915_power_well_desc > vlv_power_wells[] = { > VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > .ops = &vlv_dpio_power_well_ops, > - .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, > + .id = DISP_PW_ID_NONE, > { > .vlv.idx = > PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01, > }, > @@ -2222,7 +2222,7 @@ static const struct i915_power_well_desc > vlv_power_wells[] = { > VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > .ops = &vlv_dpio_power_well_ops, > - .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, > + .id = DISP_PW_ID_NONE, > { > .vlv.idx = > PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23, > }, > @@ -2234,7 +2234,7 @@ static const struct i915_power_well_desc > vlv_power_wells[] = { > VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > .ops = &vlv_dpio_power_well_ops, > - .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, > + .id = DISP_PW_ID_NONE, > { > .vlv.idx = > PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01, > }, > @@ -2246,7 +2246,7 @@ static const struct i915_power_well_desc > vlv_power_wells[] = { > VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > .ops = &vlv_dpio_power_well_ops, > - .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, > + .id = DISP_PW_ID_NONE, > { > .vlv.idx = > PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23, > }, > @@ -2268,7 +2268,7 @@ static const struct i915_power_well_desc > chv_power_wells[] = { > .always_on = 1, > .domains = POWER_DOMAIN_MASK, > .ops = &i9xx_always_on_power_well_ops, > - .id = I915_DISP_PW_ALWAYS_ON, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "display", > @@ -2279,7 +2279,7 @@ static const struct i915_power_well_desc > chv_power_wells[] = { > */ > .domains = CHV_DISPLAY_POWER_DOMAINS, > .ops = &chv_pipe_power_well_ops, > - .id = CHV_DISP_PW_PIPE_A, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "dpio-common-bc", > @@ -2319,7 +2319,7 @@ static const struct i915_power_well_desc > skl_power_wells[] = { > .always_on = 1, > .domains = POWER_DOMAIN_MASK, > .ops = &i9xx_always_on_power_well_ops, > - .id = I915_DISP_PW_ALWAYS_ON, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "power well 1", > @@ -2348,7 +2348,7 @@ static const struct i915_power_well_desc > skl_power_wells[] = { > .name = "DC off", > .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, > .ops = &gen9_dc_off_power_well_ops, > - .id = SKL_DISP_PW_DC_OFF, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "power well 2", > @@ -2367,7 +2367,7 @@ static const struct i915_power_well_desc > skl_power_wells[] = { > .name = "DDI A/E IO power well", > .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = SKL_DISP_PW_DDI_A_E, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E, > @@ -2377,7 +2377,7 @@ static const struct i915_power_well_desc > skl_power_wells[] = { > .name = "DDI B IO power well", > .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = SKL_DISP_PW_DDI_B, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = SKL_PW_CTL_IDX_DDI_B, > @@ -2387,7 +2387,7 @@ static const struct i915_power_well_desc > skl_power_wells[] = { > .name = "DDI C IO power well", > .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = SKL_DISP_PW_DDI_C, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = SKL_PW_CTL_IDX_DDI_C, > @@ -2397,7 +2397,7 @@ static const struct i915_power_well_desc > skl_power_wells[] = { > .name = "DDI D IO power well", > .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = SKL_DISP_PW_DDI_D, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = SKL_PW_CTL_IDX_DDI_D, > @@ -2411,7 +2411,7 @@ static const struct i915_power_well_desc > bxt_power_wells[] = { > .always_on = 1, > .domains = POWER_DOMAIN_MASK, > .ops = &i9xx_always_on_power_well_ops, > - .id = I915_DISP_PW_ALWAYS_ON, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "power well 1", > @@ -2428,7 +2428,7 @@ static const struct i915_power_well_desc > bxt_power_wells[] = { > .name = "DC off", > .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, > .ops = &gen9_dc_off_power_well_ops, > - .id = SKL_DISP_PW_DC_OFF, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "power well 2", > @@ -2469,7 +2469,7 @@ static const struct i915_power_well_desc > glk_power_wells[] = { > .always_on = 1, > .domains = POWER_DOMAIN_MASK, > .ops = &i9xx_always_on_power_well_ops, > - .id = I915_DISP_PW_ALWAYS_ON, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "power well 1", > @@ -2487,7 +2487,7 @@ static const struct i915_power_well_desc > glk_power_wells[] = { > .name = "DC off", > .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS, > .ops = &gen9_dc_off_power_well_ops, > - .id = SKL_DISP_PW_DC_OFF, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "power well 2", > @@ -2533,7 +2533,7 @@ static const struct i915_power_well_desc > glk_power_wells[] = { > .name = "AUX A", > .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = GLK_DISP_PW_AUX_A, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = GLK_PW_CTL_IDX_AUX_A, > @@ -2543,7 +2543,7 @@ static const struct i915_power_well_desc > glk_power_wells[] = { > .name = "AUX B", > .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = GLK_DISP_PW_AUX_B, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = GLK_PW_CTL_IDX_AUX_B, > @@ -2553,7 +2553,7 @@ static const struct i915_power_well_desc > glk_power_wells[] = { > .name = "AUX C", > .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = GLK_DISP_PW_AUX_C, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = GLK_PW_CTL_IDX_AUX_C, > @@ -2563,7 +2563,7 @@ static const struct i915_power_well_desc > glk_power_wells[] = { > .name = "DDI A IO power well", > .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = GLK_DISP_PW_DDI_A, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = GLK_PW_CTL_IDX_DDI_A, > @@ -2573,7 +2573,7 @@ static const struct i915_power_well_desc > glk_power_wells[] = { > .name = "DDI B IO power well", > .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = SKL_DISP_PW_DDI_B, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = SKL_PW_CTL_IDX_DDI_B, > @@ -2583,7 +2583,7 @@ static const struct i915_power_well_desc > glk_power_wells[] = { > .name = "DDI C IO power well", > .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = SKL_DISP_PW_DDI_C, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = SKL_PW_CTL_IDX_DDI_C, > @@ -2597,7 +2597,7 @@ static const struct i915_power_well_desc > cnl_power_wells[] = { > .always_on = 1, > .domains = POWER_DOMAIN_MASK, > .ops = &i9xx_always_on_power_well_ops, > - .id = I915_DISP_PW_ALWAYS_ON, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "power well 1", > @@ -2615,7 +2615,7 @@ static const struct i915_power_well_desc > cnl_power_wells[] = { > .name = "AUX A", > .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = CNL_DISP_PW_AUX_A, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = GLK_PW_CTL_IDX_AUX_A, > @@ -2625,7 +2625,7 @@ static const struct i915_power_well_desc > cnl_power_wells[] = { > .name = "AUX B", > .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = CNL_DISP_PW_AUX_B, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = GLK_PW_CTL_IDX_AUX_B, > @@ -2635,7 +2635,7 @@ static const struct i915_power_well_desc > cnl_power_wells[] = { > .name = "AUX C", > .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = CNL_DISP_PW_AUX_C, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = GLK_PW_CTL_IDX_AUX_C, > @@ -2645,7 +2645,7 @@ static const struct i915_power_well_desc > cnl_power_wells[] = { > .name = "AUX D", > .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = CNL_DISP_PW_AUX_D, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = CNL_PW_CTL_IDX_AUX_D, > @@ -2655,7 +2655,7 @@ static const struct i915_power_well_desc > cnl_power_wells[] = { > .name = "DC off", > .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS, > .ops = &gen9_dc_off_power_well_ops, > - .id = SKL_DISP_PW_DC_OFF, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "power well 2", > @@ -2674,7 +2674,7 @@ static const struct i915_power_well_desc > cnl_power_wells[] = { > .name = "DDI A IO power well", > .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = CNL_DISP_PW_DDI_A, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = GLK_PW_CTL_IDX_DDI_A, > @@ -2684,7 +2684,7 @@ static const struct i915_power_well_desc > cnl_power_wells[] = { > .name = "DDI B IO power well", > .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = SKL_DISP_PW_DDI_B, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = SKL_PW_CTL_IDX_DDI_B, > @@ -2694,7 +2694,7 @@ static const struct i915_power_well_desc > cnl_power_wells[] = { > .name = "DDI C IO power well", > .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = SKL_DISP_PW_DDI_C, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = SKL_PW_CTL_IDX_DDI_C, > @@ -2704,7 +2704,7 @@ static const struct i915_power_well_desc > cnl_power_wells[] = { > .name = "DDI D IO power well", > .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = SKL_DISP_PW_DDI_D, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = SKL_PW_CTL_IDX_DDI_D, > @@ -2714,7 +2714,7 @@ static const struct i915_power_well_desc > cnl_power_wells[] = { > .name = "DDI F IO power well", > .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = CNL_DISP_PW_DDI_F, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = CNL_PW_CTL_IDX_DDI_F, > @@ -2724,7 +2724,7 @@ static const struct i915_power_well_desc > cnl_power_wells[] = { > .name = "AUX F", > .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = CNL_DISP_PW_AUX_F, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = CNL_PW_CTL_IDX_AUX_F, > @@ -2757,7 +2757,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .always_on = 1, > .domains = POWER_DOMAIN_MASK, > .ops = &i9xx_always_on_power_well_ops, > - .id = I915_DISP_PW_ALWAYS_ON, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "power well 1", > @@ -2775,7 +2775,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "power well 2", > .domains = ICL_PW_2_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_2, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_PW_2, > @@ -2786,13 +2786,13 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "DC off", > .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS, > .ops = &gen9_dc_off_power_well_ops, > - .id = SKL_DISP_PW_DC_OFF, > + .id = DISP_PW_ID_NONE, > }, > { > .name = "power well 3", > .domains = ICL_PW_3_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_3, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_PW_3, > @@ -2805,7 +2805,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "DDI A IO", > .domains = ICL_DDI_IO_A_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_DDI_A, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_ddi_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_DDI_A, > @@ -2815,7 +2815,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "DDI B IO", > .domains = ICL_DDI_IO_B_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_DDI_B, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_ddi_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_DDI_B, > @@ -2825,7 +2825,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "DDI C IO", > .domains = ICL_DDI_IO_C_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_DDI_C, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_ddi_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_DDI_C, > @@ -2835,7 +2835,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "DDI D IO", > .domains = ICL_DDI_IO_D_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_DDI_D, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_ddi_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_DDI_D, > @@ -2845,7 +2845,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "DDI E IO", > .domains = ICL_DDI_IO_E_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_DDI_E, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_ddi_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_DDI_E, > @@ -2855,7 +2855,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "DDI F IO", > .domains = ICL_DDI_IO_F_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_DDI_F, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_ddi_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_DDI_F, > @@ -2865,7 +2865,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "AUX A", > .domains = ICL_AUX_A_IO_POWER_DOMAINS, > .ops = &icl_combo_phy_aux_power_well_ops, > - .id = ICL_DISP_PW_AUX_A, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_aux_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_AUX_A, > @@ -2875,7 +2875,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "AUX B", > .domains = ICL_AUX_B_IO_POWER_DOMAINS, > .ops = &icl_combo_phy_aux_power_well_ops, > - .id = ICL_DISP_PW_AUX_B, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_aux_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_AUX_B, > @@ -2885,7 +2885,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "AUX C", > .domains = ICL_AUX_C_IO_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_AUX_C, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_aux_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_AUX_C, > @@ -2895,7 +2895,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "AUX D", > .domains = ICL_AUX_D_IO_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_AUX_D, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_aux_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_AUX_D, > @@ -2905,7 +2905,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "AUX E", > .domains = ICL_AUX_E_IO_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_AUX_E, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_aux_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_AUX_E, > @@ -2915,7 +2915,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "AUX F", > .domains = ICL_AUX_F_IO_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_AUX_F, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_aux_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_AUX_F, > @@ -2925,7 +2925,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "AUX TBT1", > .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_AUX_TBT1, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_aux_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1, > @@ -2935,7 +2935,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "AUX TBT2", > .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_AUX_TBT2, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_aux_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2, > @@ -2945,7 +2945,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "AUX TBT3", > .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_AUX_TBT3, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_aux_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3, > @@ -2955,7 +2955,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "AUX TBT4", > .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_AUX_TBT4, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &icl_aux_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4, > @@ -2965,7 +2965,7 @@ static const struct i915_power_well_desc > icl_power_wells[] = { > .name = "power well 4", > .domains = ICL_PW_4_POWER_DOMAINS, > .ops = &hsw_power_well_ops, > - .id = ICL_DISP_PW_4, > + .id = DISP_PW_ID_NONE, > { > .hsw.regs = &hsw_power_well_regs, > .hsw.idx = ICL_PW_CTL_IDX_PW_4, > @@ -3045,6 +3045,9 @@ static void assert_power_well_ids_unique(struct > drm_i915_private *dev_priv) > enum i915_power_well_id id = power_domains- > >power_wells[i].desc->id; > > WARN_ON(id >= sizeof(power_well_ids) * 8); > + if (id == DISP_PW_ID_NONE) > + continue; > + Can't we just kill assert_power_well_ids_unique() now that the enum is trivial? Thanks, Paulo > WARN_ON(power_well_ids & BIT_ULL(id)); > power_well_ids |= BIT_ULL(id); > }
On Thu, Aug 02, 2018 at 02:26:56PM -0700, Paulo Zanoni wrote: > Em Sex, 2018-07-20 às 17:15 +0300, Imre Deak escreveu: > > Now that we removed dependence on the power well IDs to determine the > > control register and request/status flag offsets the only purpose of > > power well IDs is to look up power wells directly bypassing the power > > domains framework. However this direct lookup isn't needed for most > > of > > the exisiting power wells and hopefully won't be needed for any new > > power wells in the future. To make maintenance of the power well ID > > enum > > easier, don't require a unique ID for each power well, only if it's > > necessary. Remove the IDs becoming redundant this way and assign to > > all > > the corresponding power wells a new DISP_PW_ID_NONE ID. > > > > After the previous two patches the IDs don't need to have a fixed > > value, > > so remove the explicit initializers and adjust the enum's code > > comment > > accordingly. > > I would probably have kept every enum, but let's proceed with your > colors. > > More below: > > > > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Cc: Jani Nikula <jani.nikula@intel.com> > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 118 ++++---------------- > > --------- > > drivers/gpu/drm/i915/intel_runtime_pm.c | 129 ++++++++++++++++---- > > ------------ > > 2 files changed, 79 insertions(+), 168 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index b7022fb8d524..9b3635009826 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1029,117 +1029,25 @@ static inline bool > > i915_mmio_reg_valid(i915_reg_t reg) > > /* > > * i915_power_well_id: > > * > > - * Platform specific IDs used to look up power wells and - except > > for custom > > - * power wells - to define request/status register flag bit > > positions. As such > > - * the set of IDs on a given platform must be unique and except for > > custom > > - * power wells their value must stay fixed. > > + * IDs used to look up power wells. Power wells accessed directly > > bypassing > > + * the power domains framework must be assigned a unique ID. The > > rest of power > > + * wells must be assigned DISP_PW_ID_NONE. > > */ > > enum i915_power_well_id { > > - /* > > - * I830 > > - * - custom power well > > - */ > > - I830_DISP_PW_PIPES = 0, > > - > > - /* > > - * VLV/CHV > > - * - PUNIT_REG_PWRGT_CTRL (bit: id*2), > > - * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8) > > - */ > > - PUNIT_POWER_WELL_RENDER = 0, > > - PUNIT_POWER_WELL_MEDIA = 1, > > - PUNIT_POWER_WELL_DISP2D = 3, > > - PUNIT_POWER_WELL_DPIO_CMN_BC = 5, > > - PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, > > - PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, > > - PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, > > - PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, > > - PUNIT_POWER_WELL_DPIO_RX0 = 10, > > - PUNIT_POWER_WELL_DPIO_RX1 = 11, > > - PUNIT_POWER_WELL_DPIO_CMN_D = 12, > > - /* - custom power well */ > > - CHV_DISP_PW_PIPE_A, /* 13 */ > > - > > - /* > > - * HSW/BDW > > - * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: > > id*2+1) > > - */ > > - HSW_DISP_PW_GLOBAL = 15, > > - > > - /* > > - * GEN9+ > > - * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: > > id*2+1) > > - */ > > - SKL_DISP_PW_MISC_IO = 0, > > - SKL_DISP_PW_DDI_A_E, > > - GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, > > - CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, > > - SKL_DISP_PW_DDI_B, > > - SKL_DISP_PW_DDI_C, > > - SKL_DISP_PW_DDI_D, > > - CNL_DISP_PW_DDI_F = 6, > > - > > - GLK_DISP_PW_AUX_A = 8, > > - GLK_DISP_PW_AUX_B, > > - GLK_DISP_PW_AUX_C, > > - CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A, > > - CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B, > > - CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C, > > - CNL_DISP_PW_AUX_D, > > - CNL_DISP_PW_AUX_F, > > - > > - SKL_DISP_PW_1 = 14, > > + DISP_PW_ID_NONE, > > + > > + PUNIT_POWER_WELL_DISP2D, > > + PUNIT_POWER_WELL_DPIO_CMN_BC, > > + PUNIT_POWER_WELL_DPIO_CMN_D, > > + HSW_DISP_PW_GLOBAL, > > Looking up this one (from intel_hdcp.c) will fail to find any power > wells because they got changed to DISP_PW_ID_NONE. Err, thanks for catching this, will keep the original ID assigned for these power wells. > > + SKL_DISP_PW_MISC_IO, > > + SKL_DISP_PW_1, > > SKL_DISP_PW_2, > > - > > - /* - custom power wells */ > > BXT_DPIO_CMN_A, > > BXT_DPIO_CMN_BC, > > - GLK_DPIO_CMN_C, /* 18 */ > > - > > - /* > > - * GEN11+ > > - * - _HSW_PWR_WELL_CTL1-4 > > - * (status bit: (id&15)*2, req bit:(id&15)*2+1) > > - */ > > - ICL_DISP_PW_1 = 0, > > + GLK_DPIO_CMN_C, > > + ICL_DISP_PW_1, > > ICL_DISP_PW_2, > > Either we kill ICL_DISP_PW_2 or we don't switch its power wells to > DISP_PW_ID_NONE. I suppose killing ICL_DISP_PW_2 is the direction we're > moving to. Yep, missed this too. We'd need to keep an ID reserved for the ICL PW_2 power well, as it's actually accessed directly in assert_can_enable_dc5(). We'd fail the look up atm on ICL, which is a bug on its own. Keeping ICL_DISP_PW_2 assigned in this patch and switching to using SKL_DISP_PW_2 instead in the follow-up patch (removing ICL_DIsp_PW_2) fixes that. > > > > - ICL_DISP_PW_3, > > - ICL_DISP_PW_4, > > - > > - /* > > - * - _HSW_PWR_WELL_CTL_AUX1/2/4 > > - * (status bit: (id&15)*2, req bit:(id&15)*2+1) > > - */ > > - ICL_DISP_PW_AUX_A = 16, > > - ICL_DISP_PW_AUX_B, > > - ICL_DISP_PW_AUX_C, > > - ICL_DISP_PW_AUX_D, > > - ICL_DISP_PW_AUX_E, > > - ICL_DISP_PW_AUX_F, > > - > > - ICL_DISP_PW_AUX_TBT1 = 24, > > - ICL_DISP_PW_AUX_TBT2, > > - ICL_DISP_PW_AUX_TBT3, > > - ICL_DISP_PW_AUX_TBT4, > > - > > - /* > > - * - _HSW_PWR_WELL_CTL_DDI1/2/4 > > - * (status bit: (id&15)*2, req bit:(id&15)*2+1) > > - */ > > - ICL_DISP_PW_DDI_A = 32, > > - ICL_DISP_PW_DDI_B, > > - ICL_DISP_PW_DDI_C, > > - ICL_DISP_PW_DDI_D, > > - ICL_DISP_PW_DDI_E, > > - ICL_DISP_PW_DDI_F, /* 37 */ > > - > > - /* > > - * Multiple platforms. > > - * Must start following the highest ID of any platform. > > - * - custom power wells > > - */ > > - SKL_DISP_PW_DC_OFF = 38, > > - I915_DISP_PW_ALWAYS_ON, > > }; > > > > #define PUNIT_REG_PWRGT_CTRL 0x60 > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c > > b/drivers/gpu/drm/i915/intel_runtime_pm.c > > index 5527504d664f..792394d20f62 100644 > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > > @@ -2067,7 +2067,7 @@ static const struct i915_power_well_desc > > i9xx_always_on_power_well[] = { > > .always_on = 1, > > .domains = POWER_DOMAIN_MASK, > > .ops = &i9xx_always_on_power_well_ops, > > - .id = I915_DISP_PW_ALWAYS_ON, > > + .id = DISP_PW_ID_NONE, > > }, > > }; > > > > @@ -2084,13 +2084,13 @@ static const struct i915_power_well_desc > > i830_power_wells[] = { > > .always_on = 1, > > .domains = POWER_DOMAIN_MASK, > > .ops = &i9xx_always_on_power_well_ops, > > - .id = I915_DISP_PW_ALWAYS_ON, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "pipes", > > .domains = I830_PIPES_POWER_DOMAINS, > > .ops = &i830_pipes_power_well_ops, > > - .id = I830_DISP_PW_PIPES, > > + .id = DISP_PW_ID_NONE, > > }, > > }; > > > > @@ -2128,13 +2128,13 @@ static const struct i915_power_well_desc > > hsw_power_wells[] = { > > .always_on = 1, > > .domains = POWER_DOMAIN_MASK, > > .ops = &i9xx_always_on_power_well_ops, > > - .id = I915_DISP_PW_ALWAYS_ON, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "display", > > .domains = HSW_DISPLAY_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = HSW_DISP_PW_GLOBAL, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, > > @@ -2149,13 +2149,13 @@ static const struct i915_power_well_desc > > bdw_power_wells[] = { > > .always_on = 1, > > .domains = POWER_DOMAIN_MASK, > > .ops = &i9xx_always_on_power_well_ops, > > - .id = I915_DISP_PW_ALWAYS_ON, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "display", > > .domains = BDW_DISPLAY_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = HSW_DISP_PW_GLOBAL, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, > > @@ -2192,7 +2192,7 @@ static const struct i915_power_well_desc > > vlv_power_wells[] = { > > .always_on = 1, > > .domains = POWER_DOMAIN_MASK, > > .ops = &i9xx_always_on_power_well_ops, > > - .id = I915_DISP_PW_ALWAYS_ON, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "display", > > @@ -2210,7 +2210,7 @@ static const struct i915_power_well_desc > > vlv_power_wells[] = { > > VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | > > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > > .ops = &vlv_dpio_power_well_ops, > > - .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, > > + .id = DISP_PW_ID_NONE, > > { > > .vlv.idx = > > PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01, > > }, > > @@ -2222,7 +2222,7 @@ static const struct i915_power_well_desc > > vlv_power_wells[] = { > > VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | > > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > > .ops = &vlv_dpio_power_well_ops, > > - .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, > > + .id = DISP_PW_ID_NONE, > > { > > .vlv.idx = > > PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23, > > }, > > @@ -2234,7 +2234,7 @@ static const struct i915_power_well_desc > > vlv_power_wells[] = { > > VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | > > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > > .ops = &vlv_dpio_power_well_ops, > > - .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, > > + .id = DISP_PW_ID_NONE, > > { > > .vlv.idx = > > PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01, > > }, > > @@ -2246,7 +2246,7 @@ static const struct i915_power_well_desc > > vlv_power_wells[] = { > > VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | > > VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > > .ops = &vlv_dpio_power_well_ops, > > - .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, > > + .id = DISP_PW_ID_NONE, > > { > > .vlv.idx = > > PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23, > > }, > > @@ -2268,7 +2268,7 @@ static const struct i915_power_well_desc > > chv_power_wells[] = { > > .always_on = 1, > > .domains = POWER_DOMAIN_MASK, > > .ops = &i9xx_always_on_power_well_ops, > > - .id = I915_DISP_PW_ALWAYS_ON, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "display", > > @@ -2279,7 +2279,7 @@ static const struct i915_power_well_desc > > chv_power_wells[] = { > > */ > > .domains = CHV_DISPLAY_POWER_DOMAINS, > > .ops = &chv_pipe_power_well_ops, > > - .id = CHV_DISP_PW_PIPE_A, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "dpio-common-bc", > > @@ -2319,7 +2319,7 @@ static const struct i915_power_well_desc > > skl_power_wells[] = { > > .always_on = 1, > > .domains = POWER_DOMAIN_MASK, > > .ops = &i9xx_always_on_power_well_ops, > > - .id = I915_DISP_PW_ALWAYS_ON, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "power well 1", > > @@ -2348,7 +2348,7 @@ static const struct i915_power_well_desc > > skl_power_wells[] = { > > .name = "DC off", > > .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, > > .ops = &gen9_dc_off_power_well_ops, > > - .id = SKL_DISP_PW_DC_OFF, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "power well 2", > > @@ -2367,7 +2367,7 @@ static const struct i915_power_well_desc > > skl_power_wells[] = { > > .name = "DDI A/E IO power well", > > .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = SKL_DISP_PW_DDI_A_E, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E, > > @@ -2377,7 +2377,7 @@ static const struct i915_power_well_desc > > skl_power_wells[] = { > > .name = "DDI B IO power well", > > .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = SKL_DISP_PW_DDI_B, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = SKL_PW_CTL_IDX_DDI_B, > > @@ -2387,7 +2387,7 @@ static const struct i915_power_well_desc > > skl_power_wells[] = { > > .name = "DDI C IO power well", > > .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = SKL_DISP_PW_DDI_C, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = SKL_PW_CTL_IDX_DDI_C, > > @@ -2397,7 +2397,7 @@ static const struct i915_power_well_desc > > skl_power_wells[] = { > > .name = "DDI D IO power well", > > .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = SKL_DISP_PW_DDI_D, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = SKL_PW_CTL_IDX_DDI_D, > > @@ -2411,7 +2411,7 @@ static const struct i915_power_well_desc > > bxt_power_wells[] = { > > .always_on = 1, > > .domains = POWER_DOMAIN_MASK, > > .ops = &i9xx_always_on_power_well_ops, > > - .id = I915_DISP_PW_ALWAYS_ON, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "power well 1", > > @@ -2428,7 +2428,7 @@ static const struct i915_power_well_desc > > bxt_power_wells[] = { > > .name = "DC off", > > .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, > > .ops = &gen9_dc_off_power_well_ops, > > - .id = SKL_DISP_PW_DC_OFF, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "power well 2", > > @@ -2469,7 +2469,7 @@ static const struct i915_power_well_desc > > glk_power_wells[] = { > > .always_on = 1, > > .domains = POWER_DOMAIN_MASK, > > .ops = &i9xx_always_on_power_well_ops, > > - .id = I915_DISP_PW_ALWAYS_ON, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "power well 1", > > @@ -2487,7 +2487,7 @@ static const struct i915_power_well_desc > > glk_power_wells[] = { > > .name = "DC off", > > .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS, > > .ops = &gen9_dc_off_power_well_ops, > > - .id = SKL_DISP_PW_DC_OFF, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "power well 2", > > @@ -2533,7 +2533,7 @@ static const struct i915_power_well_desc > > glk_power_wells[] = { > > .name = "AUX A", > > .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = GLK_DISP_PW_AUX_A, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = GLK_PW_CTL_IDX_AUX_A, > > @@ -2543,7 +2543,7 @@ static const struct i915_power_well_desc > > glk_power_wells[] = { > > .name = "AUX B", > > .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = GLK_DISP_PW_AUX_B, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = GLK_PW_CTL_IDX_AUX_B, > > @@ -2553,7 +2553,7 @@ static const struct i915_power_well_desc > > glk_power_wells[] = { > > .name = "AUX C", > > .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = GLK_DISP_PW_AUX_C, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = GLK_PW_CTL_IDX_AUX_C, > > @@ -2563,7 +2563,7 @@ static const struct i915_power_well_desc > > glk_power_wells[] = { > > .name = "DDI A IO power well", > > .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = GLK_DISP_PW_DDI_A, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = GLK_PW_CTL_IDX_DDI_A, > > @@ -2573,7 +2573,7 @@ static const struct i915_power_well_desc > > glk_power_wells[] = { > > .name = "DDI B IO power well", > > .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = SKL_DISP_PW_DDI_B, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = SKL_PW_CTL_IDX_DDI_B, > > @@ -2583,7 +2583,7 @@ static const struct i915_power_well_desc > > glk_power_wells[] = { > > .name = "DDI C IO power well", > > .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = SKL_DISP_PW_DDI_C, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = SKL_PW_CTL_IDX_DDI_C, > > @@ -2597,7 +2597,7 @@ static const struct i915_power_well_desc > > cnl_power_wells[] = { > > .always_on = 1, > > .domains = POWER_DOMAIN_MASK, > > .ops = &i9xx_always_on_power_well_ops, > > - .id = I915_DISP_PW_ALWAYS_ON, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "power well 1", > > @@ -2615,7 +2615,7 @@ static const struct i915_power_well_desc > > cnl_power_wells[] = { > > .name = "AUX A", > > .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = CNL_DISP_PW_AUX_A, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = GLK_PW_CTL_IDX_AUX_A, > > @@ -2625,7 +2625,7 @@ static const struct i915_power_well_desc > > cnl_power_wells[] = { > > .name = "AUX B", > > .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = CNL_DISP_PW_AUX_B, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = GLK_PW_CTL_IDX_AUX_B, > > @@ -2635,7 +2635,7 @@ static const struct i915_power_well_desc > > cnl_power_wells[] = { > > .name = "AUX C", > > .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = CNL_DISP_PW_AUX_C, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = GLK_PW_CTL_IDX_AUX_C, > > @@ -2645,7 +2645,7 @@ static const struct i915_power_well_desc > > cnl_power_wells[] = { > > .name = "AUX D", > > .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = CNL_DISP_PW_AUX_D, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = CNL_PW_CTL_IDX_AUX_D, > > @@ -2655,7 +2655,7 @@ static const struct i915_power_well_desc > > cnl_power_wells[] = { > > .name = "DC off", > > .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS, > > .ops = &gen9_dc_off_power_well_ops, > > - .id = SKL_DISP_PW_DC_OFF, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "power well 2", > > @@ -2674,7 +2674,7 @@ static const struct i915_power_well_desc > > cnl_power_wells[] = { > > .name = "DDI A IO power well", > > .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = CNL_DISP_PW_DDI_A, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = GLK_PW_CTL_IDX_DDI_A, > > @@ -2684,7 +2684,7 @@ static const struct i915_power_well_desc > > cnl_power_wells[] = { > > .name = "DDI B IO power well", > > .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = SKL_DISP_PW_DDI_B, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = SKL_PW_CTL_IDX_DDI_B, > > @@ -2694,7 +2694,7 @@ static const struct i915_power_well_desc > > cnl_power_wells[] = { > > .name = "DDI C IO power well", > > .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = SKL_DISP_PW_DDI_C, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = SKL_PW_CTL_IDX_DDI_C, > > @@ -2704,7 +2704,7 @@ static const struct i915_power_well_desc > > cnl_power_wells[] = { > > .name = "DDI D IO power well", > > .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = SKL_DISP_PW_DDI_D, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = SKL_PW_CTL_IDX_DDI_D, > > @@ -2714,7 +2714,7 @@ static const struct i915_power_well_desc > > cnl_power_wells[] = { > > .name = "DDI F IO power well", > > .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = CNL_DISP_PW_DDI_F, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = CNL_PW_CTL_IDX_DDI_F, > > @@ -2724,7 +2724,7 @@ static const struct i915_power_well_desc > > cnl_power_wells[] = { > > .name = "AUX F", > > .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = CNL_DISP_PW_AUX_F, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = CNL_PW_CTL_IDX_AUX_F, > > @@ -2757,7 +2757,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .always_on = 1, > > .domains = POWER_DOMAIN_MASK, > > .ops = &i9xx_always_on_power_well_ops, > > - .id = I915_DISP_PW_ALWAYS_ON, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "power well 1", > > @@ -2775,7 +2775,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "power well 2", > > .domains = ICL_PW_2_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_2, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_PW_2, > > @@ -2786,13 +2786,13 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "DC off", > > .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS, > > .ops = &gen9_dc_off_power_well_ops, > > - .id = SKL_DISP_PW_DC_OFF, > > + .id = DISP_PW_ID_NONE, > > }, > > { > > .name = "power well 3", > > .domains = ICL_PW_3_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_3, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_PW_3, > > @@ -2805,7 +2805,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "DDI A IO", > > .domains = ICL_DDI_IO_A_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_DDI_A, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_ddi_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_DDI_A, > > @@ -2815,7 +2815,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "DDI B IO", > > .domains = ICL_DDI_IO_B_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_DDI_B, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_ddi_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_DDI_B, > > @@ -2825,7 +2825,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "DDI C IO", > > .domains = ICL_DDI_IO_C_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_DDI_C, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_ddi_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_DDI_C, > > @@ -2835,7 +2835,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "DDI D IO", > > .domains = ICL_DDI_IO_D_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_DDI_D, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_ddi_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_DDI_D, > > @@ -2845,7 +2845,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "DDI E IO", > > .domains = ICL_DDI_IO_E_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_DDI_E, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_ddi_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_DDI_E, > > @@ -2855,7 +2855,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "DDI F IO", > > .domains = ICL_DDI_IO_F_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_DDI_F, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_ddi_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_DDI_F, > > @@ -2865,7 +2865,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "AUX A", > > .domains = ICL_AUX_A_IO_POWER_DOMAINS, > > .ops = &icl_combo_phy_aux_power_well_ops, > > - .id = ICL_DISP_PW_AUX_A, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_aux_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_AUX_A, > > @@ -2875,7 +2875,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "AUX B", > > .domains = ICL_AUX_B_IO_POWER_DOMAINS, > > .ops = &icl_combo_phy_aux_power_well_ops, > > - .id = ICL_DISP_PW_AUX_B, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_aux_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_AUX_B, > > @@ -2885,7 +2885,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "AUX C", > > .domains = ICL_AUX_C_IO_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_AUX_C, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_aux_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_AUX_C, > > @@ -2895,7 +2895,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "AUX D", > > .domains = ICL_AUX_D_IO_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_AUX_D, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_aux_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_AUX_D, > > @@ -2905,7 +2905,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "AUX E", > > .domains = ICL_AUX_E_IO_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_AUX_E, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_aux_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_AUX_E, > > @@ -2915,7 +2915,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "AUX F", > > .domains = ICL_AUX_F_IO_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_AUX_F, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_aux_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_AUX_F, > > @@ -2925,7 +2925,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "AUX TBT1", > > .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_AUX_TBT1, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_aux_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1, > > @@ -2935,7 +2935,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "AUX TBT2", > > .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_AUX_TBT2, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_aux_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2, > > @@ -2945,7 +2945,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "AUX TBT3", > > .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_AUX_TBT3, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_aux_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3, > > @@ -2955,7 +2955,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "AUX TBT4", > > .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_AUX_TBT4, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &icl_aux_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4, > > @@ -2965,7 +2965,7 @@ static const struct i915_power_well_desc > > icl_power_wells[] = { > > .name = "power well 4", > > .domains = ICL_PW_4_POWER_DOMAINS, > > .ops = &hsw_power_well_ops, > > - .id = ICL_DISP_PW_4, > > + .id = DISP_PW_ID_NONE, > > { > > .hsw.regs = &hsw_power_well_regs, > > .hsw.idx = ICL_PW_CTL_IDX_PW_4, > > @@ -3045,6 +3045,9 @@ static void assert_power_well_ids_unique(struct > > drm_i915_private *dev_priv) > > enum i915_power_well_id id = power_domains- > > >power_wells[i].desc->id; > > > > WARN_ON(id >= sizeof(power_well_ids) * 8); > > + if (id == DISP_PW_ID_NONE) > > + continue; > > + > > Can't we just kill assert_power_well_ids_unique() now that the enum is > trivial? Yea, removing the explicit enum values makes things more trivial, but we could still assign the same enum value to different power wells. But now that you mentioned after the constify patch we could do this more easily in __set_power_wells() where we go through the power well array anyway, so can move the check there. > > Thanks, > Paulo > > > WARN_ON(power_well_ids & BIT_ULL(id)); > > power_well_ids |= BIT_ULL(id); > > }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b7022fb8d524..9b3635009826 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1029,117 +1029,25 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) /* * i915_power_well_id: * - * Platform specific IDs used to look up power wells and - except for custom - * power wells - to define request/status register flag bit positions. As such - * the set of IDs on a given platform must be unique and except for custom - * power wells their value must stay fixed. + * IDs used to look up power wells. Power wells accessed directly bypassing + * the power domains framework must be assigned a unique ID. The rest of power + * wells must be assigned DISP_PW_ID_NONE. */ enum i915_power_well_id { - /* - * I830 - * - custom power well - */ - I830_DISP_PW_PIPES = 0, - - /* - * VLV/CHV - * - PUNIT_REG_PWRGT_CTRL (bit: id*2), - * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8) - */ - PUNIT_POWER_WELL_RENDER = 0, - PUNIT_POWER_WELL_MEDIA = 1, - PUNIT_POWER_WELL_DISP2D = 3, - PUNIT_POWER_WELL_DPIO_CMN_BC = 5, - PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, - PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, - PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, - PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, - PUNIT_POWER_WELL_DPIO_RX0 = 10, - PUNIT_POWER_WELL_DPIO_RX1 = 11, - PUNIT_POWER_WELL_DPIO_CMN_D = 12, - /* - custom power well */ - CHV_DISP_PW_PIPE_A, /* 13 */ - - /* - * HSW/BDW - * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: id*2+1) - */ - HSW_DISP_PW_GLOBAL = 15, - - /* - * GEN9+ - * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: id*2+1) - */ - SKL_DISP_PW_MISC_IO = 0, - SKL_DISP_PW_DDI_A_E, - GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, - CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, - SKL_DISP_PW_DDI_B, - SKL_DISP_PW_DDI_C, - SKL_DISP_PW_DDI_D, - CNL_DISP_PW_DDI_F = 6, - - GLK_DISP_PW_AUX_A = 8, - GLK_DISP_PW_AUX_B, - GLK_DISP_PW_AUX_C, - CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A, - CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B, - CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C, - CNL_DISP_PW_AUX_D, - CNL_DISP_PW_AUX_F, - - SKL_DISP_PW_1 = 14, + DISP_PW_ID_NONE, + + PUNIT_POWER_WELL_DISP2D, + PUNIT_POWER_WELL_DPIO_CMN_BC, + PUNIT_POWER_WELL_DPIO_CMN_D, + HSW_DISP_PW_GLOBAL, + SKL_DISP_PW_MISC_IO, + SKL_DISP_PW_1, SKL_DISP_PW_2, - - /* - custom power wells */ BXT_DPIO_CMN_A, BXT_DPIO_CMN_BC, - GLK_DPIO_CMN_C, /* 18 */ - - /* - * GEN11+ - * - _HSW_PWR_WELL_CTL1-4 - * (status bit: (id&15)*2, req bit:(id&15)*2+1) - */ - ICL_DISP_PW_1 = 0, + GLK_DPIO_CMN_C, + ICL_DISP_PW_1, ICL_DISP_PW_2, - ICL_DISP_PW_3, - ICL_DISP_PW_4, - - /* - * - _HSW_PWR_WELL_CTL_AUX1/2/4 - * (status bit: (id&15)*2, req bit:(id&15)*2+1) - */ - ICL_DISP_PW_AUX_A = 16, - ICL_DISP_PW_AUX_B, - ICL_DISP_PW_AUX_C, - ICL_DISP_PW_AUX_D, - ICL_DISP_PW_AUX_E, - ICL_DISP_PW_AUX_F, - - ICL_DISP_PW_AUX_TBT1 = 24, - ICL_DISP_PW_AUX_TBT2, - ICL_DISP_PW_AUX_TBT3, - ICL_DISP_PW_AUX_TBT4, - - /* - * - _HSW_PWR_WELL_CTL_DDI1/2/4 - * (status bit: (id&15)*2, req bit:(id&15)*2+1) - */ - ICL_DISP_PW_DDI_A = 32, - ICL_DISP_PW_DDI_B, - ICL_DISP_PW_DDI_C, - ICL_DISP_PW_DDI_D, - ICL_DISP_PW_DDI_E, - ICL_DISP_PW_DDI_F, /* 37 */ - - /* - * Multiple platforms. - * Must start following the highest ID of any platform. - * - custom power wells - */ - SKL_DISP_PW_DC_OFF = 38, - I915_DISP_PW_ALWAYS_ON, }; #define PUNIT_REG_PWRGT_CTRL 0x60 diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 5527504d664f..792394d20f62 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -2067,7 +2067,7 @@ static const struct i915_power_well_desc i9xx_always_on_power_well[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = I915_DISP_PW_ALWAYS_ON, + .id = DISP_PW_ID_NONE, }, }; @@ -2084,13 +2084,13 @@ static const struct i915_power_well_desc i830_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = I915_DISP_PW_ALWAYS_ON, + .id = DISP_PW_ID_NONE, }, { .name = "pipes", .domains = I830_PIPES_POWER_DOMAINS, .ops = &i830_pipes_power_well_ops, - .id = I830_DISP_PW_PIPES, + .id = DISP_PW_ID_NONE, }, }; @@ -2128,13 +2128,13 @@ static const struct i915_power_well_desc hsw_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = I915_DISP_PW_ALWAYS_ON, + .id = DISP_PW_ID_NONE, }, { .name = "display", .domains = HSW_DISPLAY_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = HSW_DISP_PW_GLOBAL, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, @@ -2149,13 +2149,13 @@ static const struct i915_power_well_desc bdw_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = I915_DISP_PW_ALWAYS_ON, + .id = DISP_PW_ID_NONE, }, { .name = "display", .domains = BDW_DISPLAY_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = HSW_DISP_PW_GLOBAL, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, @@ -2192,7 +2192,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = I915_DISP_PW_ALWAYS_ON, + .id = DISP_PW_ID_NONE, }, { .name = "display", @@ -2210,7 +2210,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = { VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, .ops = &vlv_dpio_power_well_ops, - .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, + .id = DISP_PW_ID_NONE, { .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01, }, @@ -2222,7 +2222,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = { VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, .ops = &vlv_dpio_power_well_ops, - .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, + .id = DISP_PW_ID_NONE, { .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23, }, @@ -2234,7 +2234,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = { VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, .ops = &vlv_dpio_power_well_ops, - .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, + .id = DISP_PW_ID_NONE, { .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01, }, @@ -2246,7 +2246,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = { VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, .ops = &vlv_dpio_power_well_ops, - .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, + .id = DISP_PW_ID_NONE, { .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23, }, @@ -2268,7 +2268,7 @@ static const struct i915_power_well_desc chv_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = I915_DISP_PW_ALWAYS_ON, + .id = DISP_PW_ID_NONE, }, { .name = "display", @@ -2279,7 +2279,7 @@ static const struct i915_power_well_desc chv_power_wells[] = { */ .domains = CHV_DISPLAY_POWER_DOMAINS, .ops = &chv_pipe_power_well_ops, - .id = CHV_DISP_PW_PIPE_A, + .id = DISP_PW_ID_NONE, }, { .name = "dpio-common-bc", @@ -2319,7 +2319,7 @@ static const struct i915_power_well_desc skl_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = I915_DISP_PW_ALWAYS_ON, + .id = DISP_PW_ID_NONE, }, { .name = "power well 1", @@ -2348,7 +2348,7 @@ static const struct i915_power_well_desc skl_power_wells[] = { .name = "DC off", .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, .ops = &gen9_dc_off_power_well_ops, - .id = SKL_DISP_PW_DC_OFF, + .id = DISP_PW_ID_NONE, }, { .name = "power well 2", @@ -2367,7 +2367,7 @@ static const struct i915_power_well_desc skl_power_wells[] = { .name = "DDI A/E IO power well", .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = SKL_DISP_PW_DDI_A_E, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E, @@ -2377,7 +2377,7 @@ static const struct i915_power_well_desc skl_power_wells[] = { .name = "DDI B IO power well", .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = SKL_DISP_PW_DDI_B, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = SKL_PW_CTL_IDX_DDI_B, @@ -2387,7 +2387,7 @@ static const struct i915_power_well_desc skl_power_wells[] = { .name = "DDI C IO power well", .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = SKL_DISP_PW_DDI_C, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = SKL_PW_CTL_IDX_DDI_C, @@ -2397,7 +2397,7 @@ static const struct i915_power_well_desc skl_power_wells[] = { .name = "DDI D IO power well", .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = SKL_DISP_PW_DDI_D, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = SKL_PW_CTL_IDX_DDI_D, @@ -2411,7 +2411,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = I915_DISP_PW_ALWAYS_ON, + .id = DISP_PW_ID_NONE, }, { .name = "power well 1", @@ -2428,7 +2428,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = { .name = "DC off", .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, .ops = &gen9_dc_off_power_well_ops, - .id = SKL_DISP_PW_DC_OFF, + .id = DISP_PW_ID_NONE, }, { .name = "power well 2", @@ -2469,7 +2469,7 @@ static const struct i915_power_well_desc glk_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = I915_DISP_PW_ALWAYS_ON, + .id = DISP_PW_ID_NONE, }, { .name = "power well 1", @@ -2487,7 +2487,7 @@ static const struct i915_power_well_desc glk_power_wells[] = { .name = "DC off", .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS, .ops = &gen9_dc_off_power_well_ops, - .id = SKL_DISP_PW_DC_OFF, + .id = DISP_PW_ID_NONE, }, { .name = "power well 2", @@ -2533,7 +2533,7 @@ static const struct i915_power_well_desc glk_power_wells[] = { .name = "AUX A", .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = GLK_DISP_PW_AUX_A, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = GLK_PW_CTL_IDX_AUX_A, @@ -2543,7 +2543,7 @@ static const struct i915_power_well_desc glk_power_wells[] = { .name = "AUX B", .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = GLK_DISP_PW_AUX_B, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = GLK_PW_CTL_IDX_AUX_B, @@ -2553,7 +2553,7 @@ static const struct i915_power_well_desc glk_power_wells[] = { .name = "AUX C", .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = GLK_DISP_PW_AUX_C, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = GLK_PW_CTL_IDX_AUX_C, @@ -2563,7 +2563,7 @@ static const struct i915_power_well_desc glk_power_wells[] = { .name = "DDI A IO power well", .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = GLK_DISP_PW_DDI_A, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = GLK_PW_CTL_IDX_DDI_A, @@ -2573,7 +2573,7 @@ static const struct i915_power_well_desc glk_power_wells[] = { .name = "DDI B IO power well", .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = SKL_DISP_PW_DDI_B, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = SKL_PW_CTL_IDX_DDI_B, @@ -2583,7 +2583,7 @@ static const struct i915_power_well_desc glk_power_wells[] = { .name = "DDI C IO power well", .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = SKL_DISP_PW_DDI_C, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = SKL_PW_CTL_IDX_DDI_C, @@ -2597,7 +2597,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = I915_DISP_PW_ALWAYS_ON, + .id = DISP_PW_ID_NONE, }, { .name = "power well 1", @@ -2615,7 +2615,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = { .name = "AUX A", .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = CNL_DISP_PW_AUX_A, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = GLK_PW_CTL_IDX_AUX_A, @@ -2625,7 +2625,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = { .name = "AUX B", .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = CNL_DISP_PW_AUX_B, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = GLK_PW_CTL_IDX_AUX_B, @@ -2635,7 +2635,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = { .name = "AUX C", .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = CNL_DISP_PW_AUX_C, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = GLK_PW_CTL_IDX_AUX_C, @@ -2645,7 +2645,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = { .name = "AUX D", .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = CNL_DISP_PW_AUX_D, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = CNL_PW_CTL_IDX_AUX_D, @@ -2655,7 +2655,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = { .name = "DC off", .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS, .ops = &gen9_dc_off_power_well_ops, - .id = SKL_DISP_PW_DC_OFF, + .id = DISP_PW_ID_NONE, }, { .name = "power well 2", @@ -2674,7 +2674,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = { .name = "DDI A IO power well", .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = CNL_DISP_PW_DDI_A, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = GLK_PW_CTL_IDX_DDI_A, @@ -2684,7 +2684,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = { .name = "DDI B IO power well", .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = SKL_DISP_PW_DDI_B, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = SKL_PW_CTL_IDX_DDI_B, @@ -2694,7 +2694,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = { .name = "DDI C IO power well", .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = SKL_DISP_PW_DDI_C, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = SKL_PW_CTL_IDX_DDI_C, @@ -2704,7 +2704,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = { .name = "DDI D IO power well", .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = SKL_DISP_PW_DDI_D, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = SKL_PW_CTL_IDX_DDI_D, @@ -2714,7 +2714,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = { .name = "DDI F IO power well", .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = CNL_DISP_PW_DDI_F, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = CNL_PW_CTL_IDX_DDI_F, @@ -2724,7 +2724,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = { .name = "AUX F", .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = CNL_DISP_PW_AUX_F, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = CNL_PW_CTL_IDX_AUX_F, @@ -2757,7 +2757,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = I915_DISP_PW_ALWAYS_ON, + .id = DISP_PW_ID_NONE, }, { .name = "power well 1", @@ -2775,7 +2775,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "power well 2", .domains = ICL_PW_2_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_2, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_PW_2, @@ -2786,13 +2786,13 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "DC off", .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS, .ops = &gen9_dc_off_power_well_ops, - .id = SKL_DISP_PW_DC_OFF, + .id = DISP_PW_ID_NONE, }, { .name = "power well 3", .domains = ICL_PW_3_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_3, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_PW_3, @@ -2805,7 +2805,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "DDI A IO", .domains = ICL_DDI_IO_A_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_DDI_A, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_ddi_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_DDI_A, @@ -2815,7 +2815,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "DDI B IO", .domains = ICL_DDI_IO_B_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_DDI_B, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_ddi_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_DDI_B, @@ -2825,7 +2825,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "DDI C IO", .domains = ICL_DDI_IO_C_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_DDI_C, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_ddi_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_DDI_C, @@ -2835,7 +2835,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "DDI D IO", .domains = ICL_DDI_IO_D_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_DDI_D, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_ddi_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_DDI_D, @@ -2845,7 +2845,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "DDI E IO", .domains = ICL_DDI_IO_E_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_DDI_E, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_ddi_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_DDI_E, @@ -2855,7 +2855,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "DDI F IO", .domains = ICL_DDI_IO_F_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_DDI_F, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_ddi_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_DDI_F, @@ -2865,7 +2865,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "AUX A", .domains = ICL_AUX_A_IO_POWER_DOMAINS, .ops = &icl_combo_phy_aux_power_well_ops, - .id = ICL_DISP_PW_AUX_A, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_aux_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_AUX_A, @@ -2875,7 +2875,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "AUX B", .domains = ICL_AUX_B_IO_POWER_DOMAINS, .ops = &icl_combo_phy_aux_power_well_ops, - .id = ICL_DISP_PW_AUX_B, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_aux_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_AUX_B, @@ -2885,7 +2885,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "AUX C", .domains = ICL_AUX_C_IO_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_AUX_C, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_aux_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_AUX_C, @@ -2895,7 +2895,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "AUX D", .domains = ICL_AUX_D_IO_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_AUX_D, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_aux_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_AUX_D, @@ -2905,7 +2905,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "AUX E", .domains = ICL_AUX_E_IO_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_AUX_E, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_aux_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_AUX_E, @@ -2915,7 +2915,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "AUX F", .domains = ICL_AUX_F_IO_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_AUX_F, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_aux_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_AUX_F, @@ -2925,7 +2925,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "AUX TBT1", .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_AUX_TBT1, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_aux_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1, @@ -2935,7 +2935,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "AUX TBT2", .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_AUX_TBT2, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_aux_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2, @@ -2945,7 +2945,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "AUX TBT3", .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_AUX_TBT3, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_aux_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3, @@ -2955,7 +2955,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "AUX TBT4", .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_AUX_TBT4, + .id = DISP_PW_ID_NONE, { .hsw.regs = &icl_aux_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4, @@ -2965,7 +2965,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { .name = "power well 4", .domains = ICL_PW_4_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = ICL_DISP_PW_4, + .id = DISP_PW_ID_NONE, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_PW_4, @@ -3045,6 +3045,9 @@ static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv) enum i915_power_well_id id = power_domains->power_wells[i].desc->id; WARN_ON(id >= sizeof(power_well_ids) * 8); + if (id == DISP_PW_ID_NONE) + continue; + WARN_ON(power_well_ids & BIT_ULL(id)); power_well_ids |= BIT_ULL(id); }
Now that we removed dependence on the power well IDs to determine the control register and request/status flag offsets the only purpose of power well IDs is to look up power wells directly bypassing the power domains framework. However this direct lookup isn't needed for most of the exisiting power wells and hopefully won't be needed for any new power wells in the future. To make maintenance of the power well ID enum easier, don't require a unique ID for each power well, only if it's necessary. Remove the IDs becoming redundant this way and assign to all the corresponding power wells a new DISP_PW_ID_NONE ID. After the previous two patches the IDs don't need to have a fixed value, so remove the explicit initializers and adjust the enum's code comment accordingly. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 118 ++++------------------------- drivers/gpu/drm/i915/intel_runtime_pm.c | 129 ++++++++++++++++---------------- 2 files changed, 79 insertions(+), 168 deletions(-)