From patchwork Thu Jul 26 14:14:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Mahesh" X-Patchwork-Id: 10545957 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4702514E0 for ; Thu, 26 Jul 2018 14:12:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 35B902B3B2 for ; Thu, 26 Jul 2018 14:12:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2A35C2B3BD; Thu, 26 Jul 2018 14:12:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BC7502B3B2 for ; Thu, 26 Jul 2018 14:12:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 253F06E77E; Thu, 26 Jul 2018 14:12:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2E2046E779 for ; Thu, 26 Jul 2018 14:12:19 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jul 2018 07:12:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,405,1526367600"; d="scan'208";a="70584311" Received: from unknown (HELO localhost.localdomain) ([10.223.25.241]) by fmsmga002.fm.intel.com with ESMTP; 26 Jul 2018 07:12:17 -0700 From: Mahesh Kumar To: intel-gfx@lists.freedesktop.org Date: Thu, 26 Jul 2018 19:44:08 +0530 Message-Id: <20180726141410.2185-4-mahesh1.kumar@intel.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180726141410.2185-1-mahesh1.kumar@intel.com> References: <20180726141410.2185-1-mahesh1.kumar@intel.com> Subject: [Intel-gfx] [PATCH 3/5] drm/i915: Implement 16GB dimm wa for latency level-0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: rodrigo.vivi@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Memory with 16GB dimms require an increase of 1us in level-0 latency. This patch implements the same. Bspec: 4381 changes since V1: - s/memdev_info/dram_info - make skl_is_16gb_dimm pure function Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_drv.c | 40 ++++++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++++++ 3 files changed, 54 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index ddf6bf9b500a..86bc2e685522 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1070,6 +1070,25 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv) intel_gvt_sanitize_options(dev_priv); } +static bool +skl_is_16gb_dimm(u8 rank, u8 size, u8 width) +{ + if (size == 16 && width == SKL_DRAM_WIDTH_X8 && + rank == SKL_DRAM_RANK_SINGLE) + return true; + else if (size == 32 && width == SKL_DRAM_WIDTH_X8 && + rank == SKL_DRAM_RANK_DUAL) + return true; + else if (size == 8 && width == SKL_DRAM_WIDTH_X16 && + rank == SKL_DRAM_RANK_SINGLE) + return true; + else if (size == 16 && width == SKL_DRAM_WIDTH_X16 && + rank == SKL_DRAM_RANK_DUAL) + return true; + + return false; +} + static int skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val) { @@ -1077,6 +1096,7 @@ skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val) u8 l_size, s_size; u8 l_width, s_width; enum dram_rank rank; + bool l_16gb_dimm, s_16gb_dimm; if (!val) return -1; @@ -1103,6 +1123,13 @@ skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val) else rank = I915_DRAM_RANK_SINGLE; + l_16gb_dimm = skl_is_16gb_dimm(l_rank, l_size, l_width); + s_16gb_dimm = skl_is_16gb_dimm(s_rank, s_size, s_width); + + if (l_16gb_dimm || s_16gb_dimm) + ch->is_16gb_dimm = true; + else + ch->is_16gb_dimm = false; ch->l_info.size = l_size; ch->s_info.size = s_size; ch->l_info.width = l_width; @@ -1137,6 +1164,8 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv) return -EINVAL; } + dram_info->valid_dimm = true; + /* * If any of the channel is single rank channel, worst case output * will be same as if single rank memory, so consider single rank @@ -1152,6 +1181,10 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv) DRM_INFO("couldn't get memory rank information\n"); return -EINVAL; } + + if (ch0.is_16gb_dimm || ch1.is_16gb_dimm) + dram_info->is_16gb_dimm = true; + return 0; } @@ -1263,6 +1296,7 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv) return -EINVAL; } + dram_info->valid_dimm = true; dram_info->valid = true; return 0; } @@ -1275,6 +1309,8 @@ intel_get_dram_info(struct drm_i915_private *dev_priv) int ret; dram_info->valid = false; + dram_info->valid_dimm = false; + dram_info->is_16gb_dimm = false; dram_info->rank = I915_DRAM_RANK_INVALID; dram_info->bandwidth_kbps = 0; dram_info->num_channels = 0; @@ -1298,9 +1334,9 @@ intel_get_dram_info(struct drm_i915_private *dev_priv) sprintf(bandwidth_str, "unknown"); DRM_DEBUG_KMS("DRAM bandwidth:%s, total-channels: %u\n", bandwidth_str, dram_info->num_channels); - DRM_DEBUG_KMS("DRAM rank: %s rank\n", + DRM_DEBUG_KMS("DRAM rank: %s rank 16GB-dimm:%s\n", (dram_info->rank == I915_DRAM_RANK_DUAL) ? - "dual" : "single"); + "dual" : "single", yesno(dram_info->is_16gb_dimm)); } /** diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2d12fc152b49..854f3c828e01 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1906,6 +1906,8 @@ struct drm_i915_private { struct dram_info { bool valid; + bool valid_dimm; + bool is_16gb_dimm; u8 num_channels; enum dram_rank { I915_DRAM_RANK_INVALID = 0, @@ -2133,6 +2135,7 @@ struct dram_channel_info { u8 size, width, rank; } l_info, s_info; enum dram_rank rank; + bool is_16gb_dimm; }; static inline struct drm_i915_private *to_i915(const struct drm_device *dev) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7312ecb73415..2446f53adf21 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2874,6 +2874,19 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, } } + /* + * WA Level-0 adjustment for 16GB DIMMs: SKL+ + * If we could not get dimm info enable this WA to prevent from + * any underrun. If not able to get Dimm info assume 16GB dimm + * to avoid any underrun. + */ + if (dev_priv->dram_info.valid_dimm) { + if (dev_priv->dram_info.is_16gb_dimm) + wm[0] += 1; + } else { + wm[0] += 1; + } + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { uint64_t sskpd = I915_READ64(MCH_SSKPD);