diff mbox series

[5/5] drm/i915/skl+: don't trust IPC value set by BIOS

Message ID 20180726141410.2185-6-mahesh1.kumar@intel.com (mailing list archive)
State New, archived
Headers show
Series Decode memdev info and bandwidth and implemnt latency WA | expand

Commit Message

Kumar, Mahesh July 26, 2018, 2:14 p.m. UTC 
If KMS decide to disable IPC make sure we override IPC configuration set
by BIOS.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 39e400d5f555..77b34fe546a8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6097,10 +6097,8 @@  void intel_enable_ipc(struct drm_i915_private *dev_priv)
 	u32 val;
 
 	/* Display WA #0477 WaDisableIPC: skl */
-	if (IS_SKYLAKE(dev_priv) || !dev_priv->ipc_capable_mem) {
+	if (IS_SKYLAKE(dev_priv) || !dev_priv->ipc_capable_mem)
 		dev_priv->ipc_enabled = false;
-		return;
-	}
 
 	val = I915_READ(DISP_ARB_CTL2);