From patchwork Thu Jul 26 22:43:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10546505 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 711AE14E2 for ; Thu, 26 Jul 2018 22:44:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 511072BA8D for ; Thu, 26 Jul 2018 22:44:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 457602BBAD; Thu, 26 Jul 2018 22:44:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A9CC82BA8D for ; Thu, 26 Jul 2018 22:44:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6AA5D6E859; Thu, 26 Jul 2018 22:44:04 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id B692E6E14D for ; Thu, 26 Jul 2018 22:44:02 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jul 2018 15:44:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,406,1526367600"; d="scan'208";a="60153163" Received: from josouza-mobl.jf.intel.com ([10.24.11.40]) by orsmga008.jf.intel.com with ESMTP; 26 Jul 2018 15:43:59 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 26 Jul 2018 15:43:08 -0700 Message-Id: <20180726224314.30241-4-jose.souza@intel.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180726224314.30241-1-jose.souza@intel.com> References: <20180726224314.30241-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 04/10] drm/i915: Move out non-display related calls from display/modeset init/cleanup X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP i915_load_modeset_init() and intel_modeset_cleanup() was initializing and cleaning up things that is not display only. This will make easy initialize driver without display block. Also moving VLV/CHV/BYT czclk as it is a core clock used as base by several other GPU blocks not only display, including gem/GT. Spec: 14370 Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 86 ++++++++++++++++++---------- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_display.c | 28 ++------- drivers/gpu/drm/i915/intel_pm.c | 10 ++++ 4 files changed, 72 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 62f34f8aa02b..3ca30b9f2096 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -665,28 +665,15 @@ static int i915_load_modeset_init(struct drm_device *dev) if (ret) goto cleanup_vga_client; - /* must happen before intel_power_domains_init_hw() on VLV/CHV */ - intel_update_rawclk(dev_priv); - - intel_power_domains_init_hw(dev_priv, false); - intel_csr_ucode_init(dev_priv); - ret = intel_irq_install(dev_priv); - if (ret) - goto cleanup_csr; - intel_setup_gmbus(dev_priv); /* Important: The output setup functions called by modeset_init need * working irqs for e.g. gmbus and dp aux transfers. */ ret = intel_modeset_init(dev); if (ret) - goto cleanup_irq; - - ret = i915_gem_init(dev_priv); - if (ret) - goto cleanup_modeset; + goto cleanup_gmbus; intel_setup_overlay(dev_priv); @@ -695,25 +682,18 @@ static int i915_load_modeset_init(struct drm_device *dev) ret = intel_fbdev_init(dev); if (ret) - goto cleanup_gem; + goto cleanup_modeset; /* Only enable hotplug handling once the fbdev is fully set up. */ intel_hpd_init(dev_priv); return 0; -cleanup_gem: - if (i915_gem_suspend(dev_priv)) - DRM_ERROR("failed to idle hardware; continuing to unload!\n"); - i915_gem_fini(dev_priv); cleanup_modeset: intel_modeset_cleanup(dev); -cleanup_irq: - drm_irq_uninstall(dev); +cleanup_gmbus: intel_teardown_gmbus(dev_priv); -cleanup_csr: intel_csr_ucode_fini(dev_priv); - intel_power_domains_fini(dev_priv); vga_switcheroo_unregister_client(pdev); cleanup_vga_client: vga_client_register(pdev, NULL, NULL, NULL); @@ -1397,9 +1377,25 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) goto out_cleanup_hw; } + /* must happen before intel_power_domains_init_hw() on VLV/CHV */ + intel_update_rawclk(dev_priv); + + /* i915_gem_init() call chain will call + * intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ); + */ + intel_power_domains_init_hw(dev_priv, false); + + ret = intel_irq_install(dev_priv); + if (ret) + goto out_cleanup_power; + + ret = i915_gem_init(dev_priv); + if (ret) + goto cleanup_irq; + ret = i915_load_modeset_init(&dev_priv->drm); if (ret < 0) - goto out_cleanup_hw; + goto cleanup_gem; i915_driver_register(dev_priv); @@ -1413,6 +1409,15 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) return 0; +cleanup_gem: + if (i915_gem_suspend(dev_priv)) + DRM_ERROR("failed to idle hardware; continuing to unload!\n"); + intel_cleanup_gt_powersave(dev_priv); + i915_gem_fini(dev_priv); +cleanup_irq: + drm_irq_uninstall(&dev_priv->drm); +out_cleanup_power: + intel_power_domains_fini(dev_priv); out_cleanup_hw: i915_driver_cleanup_hw(dev_priv); out_cleanup_mmio: @@ -1431,11 +1436,24 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) return ret; } -void i915_driver_unload(struct drm_device *dev) +/* unload/cleanup the leftover of i915_load_modeset_init() */ +static void i915_modeset_unload(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); struct pci_dev *pdev = dev_priv->drm.pdev; + intel_bios_cleanup(dev_priv); + + vga_switcheroo_unregister_client(pdev); + vga_client_register(pdev, NULL, NULL, NULL); + + intel_csr_ucode_fini(dev_priv); +} + +void i915_driver_unload(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = to_i915(dev); + i915_driver_unregister(dev_priv); if (i915_gem_suspend(dev_priv)) @@ -1447,14 +1465,22 @@ void i915_driver_unload(struct drm_device *dev) intel_gvt_cleanup(dev_priv); - intel_modeset_cleanup(dev); + intel_modeset_cleanup_prepare(dev); - intel_bios_cleanup(dev_priv); + intel_disable_gt_powersave(dev_priv); - vga_switcheroo_unregister_client(pdev); - vga_client_register(pdev, NULL, NULL, NULL); + /* + * Interrupts and polling as the first thing to avoid creating havoc. + * Too much stuff here (turning of connectors, ...) would + * experience fancy races otherwise. + */ + intel_irq_uninstall(dev_priv); - intel_csr_ucode_fini(dev_priv); + intel_modeset_cleanup(dev); + + intel_cleanup_gt_powersave(dev_priv); + + i915_modeset_unload(dev); /* Free error state after interrupts are fully disabled. */ cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0f49f9988dfa..d50fd9825b10 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3411,6 +3411,7 @@ mkwrite_device_info(struct drm_i915_private *dev_priv) /* modesetting */ extern void intel_modeset_init_hw(struct drm_device *dev); extern int intel_modeset_init(struct drm_device *dev); +void intel_modeset_cleanup_prepare(struct drm_device *dev); extern void intel_modeset_cleanup(struct drm_device *dev); extern int intel_connector_register(struct drm_connector *); extern void intel_connector_unregister(struct drm_connector *); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 577b30dde45b..1b0ee796f697 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -218,17 +218,6 @@ int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, dev_priv->hpll_freq); } -static void intel_update_czclk(struct drm_i915_private *dev_priv) -{ - if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) - return; - - dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", - CCK_CZ_CLOCK_CONTROL); - - DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); -} - static inline u32 /* units of 100MHz */ intel_fdi_link_freq(struct drm_i915_private *dev_priv, const struct intel_crtc_state *pipe_config) @@ -15247,7 +15236,6 @@ int intel_modeset_init(struct drm_device *dev) intel_shared_dpll_init(dev); intel_update_fdi_pll_freq(dev_priv); - intel_update_czclk(dev_priv); intel_modeset_init_hw(dev); if (dev_priv->max_cdclk_freq == 0) @@ -15962,7 +15950,7 @@ static void intel_hpd_poll_fini(struct drm_device *dev) drm_connector_list_iter_end(&conn_iter); } -void intel_modeset_cleanup(struct drm_device *dev) +void intel_modeset_cleanup_prepare(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); @@ -15970,15 +15958,11 @@ void intel_modeset_cleanup(struct drm_device *dev) flush_work(&dev_priv->atomic_helper.free_work); WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); +} - intel_disable_gt_powersave(dev_priv); - - /* - * Interrupts and polling as the first thing to avoid creating havoc. - * Too much stuff here (turning of connectors, ...) would - * experience fancy races otherwise. - */ - intel_irq_uninstall(dev_priv); +void intel_modeset_cleanup(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = to_i915(dev); /* * Due to the hpd irq storm handling the hotplug work can re-arm the @@ -16000,8 +15984,6 @@ void intel_modeset_cleanup(struct drm_device *dev) intel_cleanup_overlay(dev_priv); - intel_cleanup_gt_powersave(dev_priv); - intel_teardown_gmbus(dev_priv); destroy_workqueue(dev_priv->modeset_wq); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7312ecb73415..e54a65405448 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7365,6 +7365,14 @@ static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv) dev_priv->gt_pm.rps.gpll_ref_freq); } +static void valleyview_update_czclk(struct drm_i915_private *dev_priv) +{ + dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", + CCK_CZ_CLOCK_CONTROL); + + DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); +} + static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv) { struct intel_rps *rps = &dev_priv->gt_pm.rps; @@ -7372,6 +7380,7 @@ static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv) valleyview_setup_pctx(dev_priv); + valleyview_update_czclk(dev_priv); vlv_init_gpll_ref_freq(dev_priv); val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); @@ -7418,6 +7427,7 @@ static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv) cherryview_setup_pctx(dev_priv); + valleyview_update_czclk(dev_priv); vlv_init_gpll_ref_freq(dev_priv); mutex_lock(&dev_priv->sb_lock);