| Message ID | 20180730164325.12770-1-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/execlists: Terminate the context image with BB_END | expand |
On 30/07/18 17:43, Chris Wilson wrote: > In the aub trace utility, the context images are terminated with a > MI_BATCH_BUFFER_END; the simulator is reported as complaining otherwise. > Do the same for our protocontext image for completeness, and in passing > apply the magic bit for gen10 to mark the end of the context image. > > Reported-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Doesn't look like anything exploded. Have you noticed any improvement maybe in the benchmarks? Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > --- > drivers/gpu/drm/i915/intel_lrc.c | 4 ++++ > drivers/gpu/drm/i915/intel_lrc_reg.h | 2 +- > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index fad689efb67a..b0be180c6294 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -2653,6 +2653,10 @@ static void execlists_init_reg_state(u32 *regs, > > i915_oa_init_reg_state(engine, ctx, regs); > } > + > + regs[CTX_END] = MI_BATCH_BUFFER_END; > + if (INTEL_GEN(dev_priv) >= 10) > + regs[CTX_END] |= BIT(0); > } > > static int > diff --git a/drivers/gpu/drm/i915/intel_lrc_reg.h b/drivers/gpu/drm/i915/intel_lrc_reg.h > index 169a2239d6c7..5ef932d810a7 100644 > --- a/drivers/gpu/drm/i915/intel_lrc_reg.h > +++ b/drivers/gpu/drm/i915/intel_lrc_reg.h > @@ -37,7 +37,7 @@ > #define CTX_PDP0_LDW 0x32 > #define CTX_LRI_HEADER_2 0x41 > #define CTX_R_PWR_CLK_STATE 0x42 > -#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 > +#define CTX_END 0x44 > > #define CTX_REG(reg_state, pos, reg, val) do { \ > u32 *reg_state__ = (reg_state); \
Quoting Lionel Landwerlin (2018-07-31 13:47:32) > On 30/07/18 17:43, Chris Wilson wrote: > > In the aub trace utility, the context images are terminated with a > > MI_BATCH_BUFFER_END; the simulator is reported as complaining otherwise. > > Do the same for our protocontext image for completeness, and in passing > > apply the magic bit for gen10 to mark the end of the context image. > > > > Reported-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > > Doesn't look like anything exploded. > Have you noticed any improvement maybe in the benchmarks? Haven't found anything that shows a difference. I expect that after the first save, the context image has grown the BB_END. I was going to dissect the default context image to see if that was true. -Chris
Quoting Lionel Landwerlin (2018-07-31 13:47:32) > On 30/07/18 17:43, Chris Wilson wrote: > > In the aub trace utility, the context images are terminated with a > > MI_BATCH_BUFFER_END; the simulator is reported as complaining otherwise. > > Do the same for our protocontext image for completeness, and in passing > > apply the magic bit for gen10 to mark the end of the context image. > > > > Reported-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > > Doesn't look like anything exploded. > Have you noticed any improvement maybe in the benchmarks? In practice, it is replaced by HW state, so it only applies to the very first context load on which it is meant to be suppressed. Interesting to note that the HW only terminates RCS with a BB_END. -Chris
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index fad689efb67a..b0be180c6294 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2653,6 +2653,10 @@ static void execlists_init_reg_state(u32 *regs, i915_oa_init_reg_state(engine, ctx, regs); } + + regs[CTX_END] = MI_BATCH_BUFFER_END; + if (INTEL_GEN(dev_priv) >= 10) + regs[CTX_END] |= BIT(0); } static int diff --git a/drivers/gpu/drm/i915/intel_lrc_reg.h b/drivers/gpu/drm/i915/intel_lrc_reg.h index 169a2239d6c7..5ef932d810a7 100644 --- a/drivers/gpu/drm/i915/intel_lrc_reg.h +++ b/drivers/gpu/drm/i915/intel_lrc_reg.h @@ -37,7 +37,7 @@ #define CTX_PDP0_LDW 0x32 #define CTX_LRI_HEADER_2 0x41 #define CTX_R_PWR_CLK_STATE 0x42 -#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 +#define CTX_END 0x44 #define CTX_REG(reg_state, pos, reg, val) do { \ u32 *reg_state__ = (reg_state); \
In the aub trace utility, the context images are terminated with a MI_BATCH_BUFFER_END; the simulator is reported as complaining otherwise. Do the same for our protocontext image for completeness, and in passing apply the magic bit for gen10 to mark the end of the context image. Reported-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 4 ++++ drivers/gpu/drm/i915/intel_lrc_reg.h | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-)