From patchwork Thu Aug 2 10:06:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 10553403 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EFA0913BF for ; Thu, 2 Aug 2018 10:06:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DA3D42BB59 for ; Thu, 2 Aug 2018 10:06:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CE7F82BB62; Thu, 2 Aug 2018 10:06:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 56AA72BB59 for ; Thu, 2 Aug 2018 10:06:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C9C096E0D4; Thu, 2 Aug 2018 10:06:47 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2225C6E0D4 for ; Thu, 2 Aug 2018 10:06:45 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 12549513-1500050 for multiple; Thu, 02 Aug 2018 11:06:32 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Thu, 2 Aug 2018 11:06:31 +0100 Message-Id: <20180802100631.31305-4-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180802100631.31305-1-chris@chris-wilson.co.uk> References: <20180802100631.31305-1-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 4/4] drm/i915: Dampen RPS slow start X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mika Kuoppala MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Currently, we note congestion for the slow start ramping up of RPS only when we overshoot the target workload and have to reverse direction for our reclocking. That is, if we have a period where the current GPU frequency is enough to sustain the workload within our target utilisation, we should not trigger any RPS EI interrupts, and then may continue again with the previous last_adj after multiple periods causing us to dramatically overreact. To prevent us not noticing a period where the system is behaving correctly, we can schedule an extra interrupt that will not be associated with either an up or down event causing to reset last_adj back to zero, cancelling the slow start due to the congestion. v2: Separate up/down EI v3: Reset rps events upon enabling Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/i915_irq.c | 43 +++++++++++++++++++++------------ drivers/gpu/drm/i915/intel_pm.c | 14 ++++++++--- 2 files changed, 38 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 8084e35b25c5..69919a97ec2e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -493,6 +493,14 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) spin_lock_irq(&dev_priv->irq_lock); WARN_ON_ONCE(rps->pm_iir); + if (IS_VALLEYVIEW(dev_priv)) + /* WaGsvRC0ResidencyMethod:vlv */ + dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; + else + dev_priv->pm_rps_events = (GEN6_PM_RP_UP_THRESHOLD | + GEN6_PM_RP_DOWN_THRESHOLD | + GEN6_PM_RP_DOWN_TIMEOUT); + if (INTEL_GEN(dev_priv) >= 11) WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM)); else @@ -1298,7 +1306,13 @@ static void gen6_pm_rps_work(struct work_struct *work) mutex_lock(&dev_priv->pcu_lock); - pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); + dev_priv->pm_rps_events &= + ~(GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED); + + if (IS_VALLEYVIEW(dev_priv)) { + dev_priv->pm_rps_events |= GEN6_PM_RP_UP_EI_EXPIRED; + pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); + } adj = rps->last_adj; new_delay = rps->cur_freq; @@ -1310,10 +1324,12 @@ static void gen6_pm_rps_work(struct work_struct *work) new_delay = rps->boost_freq; adj = 0; } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { - if (adj > 0) + if (adj > 0) { + dev_priv->pm_rps_events |= GEN6_PM_RP_UP_EI_EXPIRED; adj *= 2; - else /* CHV needs even encode values */ + } else { /* CHV needs even encode values */ adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; + } if (new_delay >= rps->max_freq_softlimit) adj = 0; @@ -1326,15 +1342,21 @@ static void gen6_pm_rps_work(struct work_struct *work) new_delay = rps->min_freq_softlimit; adj = 0; } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { - if (adj < 0) + if (adj < 0) { + dev_priv->pm_rps_events |= GEN6_PM_RP_DOWN_EI_EXPIRED; adj *= 2; - else /* CHV needs even encode values */ + } else { /* CHV needs even encode values */ adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; + } if (new_delay <= rps->min_freq_softlimit) adj = 0; - } else { /* unknown event */ + } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD && adj > 0) { + adj = 0; + } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD && adj < 0) { adj = 0; + } else { + /* unknown event */ } rps->last_adj = adj; @@ -4773,15 +4795,6 @@ void intel_irq_init(struct drm_i915_private *dev_priv) if (HAS_GUC_SCHED(dev_priv)) dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT; - /* Let's track the enabled rps events */ - if (IS_VALLEYVIEW(dev_priv)) - /* WaGsvRC0ResidencyMethod:vlv */ - dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; - else - dev_priv->pm_rps_events = (GEN6_PM_RP_UP_THRESHOLD | - GEN6_PM_RP_DOWN_THRESHOLD | - GEN6_PM_RP_DOWN_TIMEOUT); - rps->pm_intrmsk_mbz = 0; /* diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f90a3c7f1c40..d71a498ee3a1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6397,10 +6397,16 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) u32 mask = 0; /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */ - if (val > rps->min_freq_softlimit) - mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; - if (val < rps->max_freq_softlimit) - mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; + if (val > rps->min_freq_softlimit) { + mask |= (GEN6_PM_RP_UP_EI_EXPIRED | + GEN6_PM_RP_DOWN_EI_EXPIRED | + GEN6_PM_RP_DOWN_THRESHOLD | + GEN6_PM_RP_DOWN_TIMEOUT); + } + if (val < rps->max_freq_softlimit) { + mask |= (GEN6_PM_RP_UP_EI_EXPIRED | + GEN6_PM_RP_UP_THRESHOLD); + } mask &= dev_priv->pm_rps_events;