From patchwork Wed Aug 8 14:19:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maarten Lankhorst X-Patchwork-Id: 10560041 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E20311390 for ; Wed, 8 Aug 2018 14:19:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D07F92ADF9 for ; Wed, 8 Aug 2018 14:19:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C4A6E2ADFB; Wed, 8 Aug 2018 14:19:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 65E8B2ADF9 for ; Wed, 8 Aug 2018 14:19:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D636189FA5; Wed, 8 Aug 2018 14:19:16 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mblankhorst.nl (mblankhorst.nl [IPv6:2a02:2308::216:3eff:fe92:dfa3]) by gabe.freedesktop.org (Postfix) with ESMTPS id BA79789FA5 for ; Wed, 8 Aug 2018 14:19:15 +0000 (UTC) From: Maarten Lankhorst To: intel-gfx@lists.freedesktop.org Date: Wed, 8 Aug 2018 16:19:11 +0200 Message-Id: <20180808141911.7647-2-maarten.lankhorst@linux.intel.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180808141911.7647-1-maarten.lankhorst@linux.intel.com> References: <20180808141911.7647-1-maarten.lankhorst@linux.intel.com> Subject: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Add debugfs support to force a downgrade to PSR1 mode. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This will make it easier to test PSR1 on PSR2 capable eDP machines. Changes since v1: - Remove I915_PSR_DEBUG_FORCE_PSR2, it did nothing, not sure forcing PSR2 would even work. - Handle NULL crtc in intel_psr_set_debugfs_mode. (dhnkrn) Signed-off-by: Maarten Lankhorst Reviewed-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 44 ++++++++++++++++++++++++++++---- 2 files changed, 40 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a3ea48ce1811..14883614d9e6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -616,6 +616,7 @@ struct i915_psr { #define I915_PSR_DEBUG_DEFAULT 0x00 #define I915_PSR_DEBUG_DISABLE 0x01 #define I915_PSR_DEBUG_ENABLE 0x02 +#define I915_PSR_DEBUG_FORCE_PSR1 0x03 #define I915_PSR_DEBUG_IRQ 0x10 u32 debug; diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 12fbc59af5a4..a408faa16f90 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -68,6 +68,17 @@ static bool psr_global_enabled(u32 debug) } } +static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, + const struct intel_crtc_state *crtc_state) +{ + switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { + case I915_PSR_DEBUG_FORCE_PSR1: + return false; + default: + return crtc_state->has_psr2; + } +} + void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug) { u32 debug_mask, mask; @@ -646,7 +657,7 @@ void intel_psr_enable(struct intel_dp *intel_dp, goto unlock; } - dev_priv->psr.psr2_enabled = crtc_state->has_psr2; + dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); dev_priv->psr.busy_frontbuffer_bits = 0; dev_priv->psr.prepared = true; @@ -820,19 +831,38 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) return err == 0 && dev_priv->psr.enabled; } +static bool switching_psr(struct drm_i915_private *dev_priv, + struct intel_crtc_state *crtc_state, + u32 mode) +{ + /* Can't switch psr state anyway if PSR2 is not supported. */ + if (!crtc_state || !crtc_state->has_psr2) + return false; + + if (dev_priv->psr.psr2_enabled && mode == I915_PSR_DEBUG_FORCE_PSR1) + return true; + + if (!dev_priv->psr.psr2_enabled && mode != I915_PSR_DEBUG_FORCE_PSR1) + return true; + + return false; +} + int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv, struct drm_modeset_acquire_ctx *ctx, u64 val) { struct drm_device *dev = &dev_priv->drm; struct drm_connector_state *conn_state; + struct intel_crtc_state *crtc_state = NULL; struct drm_crtc *crtc; struct intel_dp *dp; int ret; bool enable; + u32 mode = val & I915_PSR_DEBUG_MODE_MASK; if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || - (val & I915_PSR_DEBUG_MODE_MASK) > I915_PSR_DEBUG_ENABLE) { + mode > I915_PSR_DEBUG_FORCE_PSR1) { DRM_DEBUG_KMS("Invalid debug mask %llx\n", val); return -EINVAL; } @@ -850,7 +880,8 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv, if (ret) return ret; - ret = wait_for_completion_interruptible(&crtc->state->commit->hw_done); + crtc_state = to_intel_crtc_state(crtc->state); + ret = wait_for_completion_interruptible(&crtc_state->base.commit->hw_done); } else ret = wait_for_completion_interruptible(&conn_state->commit->hw_done); @@ -863,14 +894,17 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv, enable = psr_global_enabled(val); - if (!enable) + if (!enable || switching_psr(dev_priv, crtc_state, mode)) intel_psr_disable_locked(dev_priv->psr.dp); dev_priv->psr.debug = val; + if (crtc) + dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); + intel_psr_irq_control(dev_priv, dev_priv->psr.debug & I915_PSR_DEBUG_IRQ); if (dev_priv->psr.prepared && enable) - intel_psr_enable_locked(dev_priv, to_intel_crtc_state(crtc->state)); + intel_psr_enable_locked(dev_priv, crtc_state); mutex_unlock(&dev_priv->psr.lock); return ret;