From patchwork Thu Aug 9 00:16:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10560667 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 225B113AC for ; Thu, 9 Aug 2018 00:17:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 163BD20952 for ; Thu, 9 Aug 2018 00:17:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0AC192AC6C; Thu, 9 Aug 2018 00:17:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AA3A520952 for ; Thu, 9 Aug 2018 00:17:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C6686E649; Thu, 9 Aug 2018 00:17:12 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id EE9E66E62F for ; Thu, 9 Aug 2018 00:16:54 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Aug 2018 17:16:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,212,1531810800"; d="scan'208";a="60976920" Received: from josouza-mobl.jf.intel.com ([10.24.11.40]) by fmsmga007.fm.intel.com with ESMTP; 08 Aug 2018 17:16:54 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Wed, 8 Aug 2018 17:16:04 -0700 Message-Id: <20180809001606.26876-18-jose.souza@intel.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180809001606.26876-1-jose.souza@intel.com> References: <20180809001606.26876-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 18/20] drm/i195: Do not initialize display core when display is disabled X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The only thing left from *_display_core_init when display is disabled is the skl_pch_reset_handshake() that is already handling display enabled and disabled. And *_display_core_uninit() also was left to disable DC. If more power savings is required, we could disable the power wells that BIOS enable. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_runtime_pm.c | 32 +++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 01e0c8e82fcf..8a84c77a1a88 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -3292,6 +3292,9 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, /* enable PCH reset handshake */ skl_pch_reset_handshake(dev_priv); + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + /* enable PG1 and Misc I/O */ mutex_lock(&power_domains->lock); @@ -3318,6 +3321,9 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv) gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + gen9_dbuf_disable(dev_priv); skl_uninit_cdclk(dev_priv); @@ -3357,6 +3363,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv, */ skl_pch_reset_handshake(dev_priv); + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + /* Enable PG1 */ mutex_lock(&power_domains->lock); @@ -3380,6 +3389,9 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv) gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + gen9_dbuf_disable(dev_priv); bxt_uninit_cdclk(dev_priv); @@ -3478,6 +3490,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume /* 1. Enable PCH Reset Handshake */ skl_pch_reset_handshake(dev_priv); + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + /* 2. Enable Comp */ val = I915_READ(CHICKEN_MISC_2); val &= ~CNL_COMP_PWR_DOWN; @@ -3522,7 +3537,10 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); - /* 1. Disable all display engine functions -> aready done */ + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + + /* 1. Disable all display engine functions -> already done */ /* 2. Disable DBUF */ gen9_dbuf_disable(dev_priv); @@ -3561,6 +3579,9 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, /* 1. Enable PCH reset handshake. */ skl_pch_reset_handshake(dev_priv); + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + for (port = PORT_A; port <= PORT_B; port++) { /* 2. Enable DDI combo PHY comp. */ val = I915_READ(ICL_PHY_MISC(port)); @@ -3607,7 +3628,10 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); - /* 1. Disable all display engine functions -> aready done */ + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + + /* 1. Disable all display engine functions -> already done */ /* 2. Disable DBUF */ icl_dbuf_disable(dev_priv); @@ -3773,11 +3797,11 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) skl_display_core_init(dev_priv, resume); } else if (IS_GEN9_LP(dev_priv)) { bxt_display_core_init(dev_priv, resume); - } else if (IS_CHERRYVIEW(dev_priv)) { + } else if (IS_CHERRYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) { mutex_lock(&power_domains->lock); chv_phy_control_init(dev_priv); mutex_unlock(&power_domains->lock); - } else if (IS_VALLEYVIEW(dev_priv)) { + } else if (IS_VALLEYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) { mutex_lock(&power_domains->lock); vlv_cmnlane_wa(dev_priv); mutex_unlock(&power_domains->lock);