From patchwork Tue Aug 14 14:40:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10565753 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 554DF13B4 for ; Tue, 14 Aug 2018 14:41:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 450AF2A106 for ; Tue, 14 Aug 2018 14:41:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 42F222A11F; Tue, 14 Aug 2018 14:41:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 36F252A10E for ; Tue, 14 Aug 2018 14:41:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 01A606E07C; Tue, 14 Aug 2018 14:41:09 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id 276686E07C for ; Tue, 14 Aug 2018 14:41:06 +0000 (UTC) Received: by mail-wm0-x243.google.com with SMTP id c14-v6so12539042wmb.4 for ; Tue, 14 Aug 2018 07:41:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dBzXjdZQYg3y2HQw3j3I50n48p/yZBpJCXKLBXHUcFU=; b=kwtN5Aq4iKTxJtq2aJI184kClv9YR+4JHmeMCocUscDJGXwtkP7pFvW0UGic+3dClb 1t7lbtpicc/XeNJGrwjGGumqIspeLUMN8Ql/3DNj3520JoqLBpUxf32bRYjjPkVzDq/K HXmmJrtyjIddc1xVYEqQ8jcgiIntFmKONA3vb7FOQ9v1gVh0+N4GixX7Ait7z5s905BR WfFRmhDZnQfZbbQ8c+gtkSo2HzfXFqk+RwtBxZ7eUOkFnD74nSDugXD6kO2pGkuS7j0G RTYBwSgg1prrqwgv4sDOYgqbLESnqVT4ZBKoyioHCJA7xe02okEXFQiGmrDSjE8Y4CFg Dc5Q== X-Gm-Message-State: AOUpUlHULvDSZthDX0WzgmMIy42Du2phuQzGOlVNmXKPHDDX95Ew7pjt l9ELPm7vuvTvWfWb0hK6PvTtxM7gtno= X-Google-Smtp-Source: AA+uWPzZxtjVRJiBx45Ij2h9j0V4lnuDCfnF5+3SXgO+VY1MQMJMRDFGLy9oZRiahnlTyFD4WuRbdw== X-Received: by 2002:a1c:e146:: with SMTP id y67-v6mr2379127wmg.108.1534257664548; Tue, 14 Aug 2018 07:41:04 -0700 (PDT) Received: from localhost.localdomain ([95.144.165.93]) by smtp.gmail.com with ESMTPSA id w17-v6sm8884719wmc.43.2018.08.14.07.41.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Aug 2018 07:41:03 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Tue, 14 Aug 2018 15:40:51 +0100 Message-Id: <20180814144058.19286-2-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180814144058.19286-1-tvrtko.ursulin@linux.intel.com> References: <20180814144058.19286-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH 1/8] drm/i915: Program RPCS for Broadwell X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Chris Wilson Currently we only configure the power gating for Skylake and above, but the configuration should equally apply to Broadwell and Braswell. Even though, there is not as much variation as for later generations, we want to expose control over the configuration to userspace and may want to opt out of the "always-enabled" setting. Signed-off-by: Chris Wilson Signed-off-by: Lionel Landwerlin Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_lrc.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 3f90c74038ef..d3ffb268a7a1 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2489,13 +2489,6 @@ make_rpcs(struct drm_i915_private *dev_priv) { u32 rpcs = 0; - /* - * No explicit RPCS request is needed to ensure full - * slice/subslice/EU enablement prior to Gen9. - */ - if (INTEL_GEN(dev_priv) < 9) - return 0; - /* * Starting in Gen9, render power gating can leave * slice/subslice/EU in a partially enabled state. We