From patchwork Tue Aug 14 14:40:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10565761 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4737B13B4 for ; Tue, 14 Aug 2018 14:41:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 35E632A0E3 for ; Tue, 14 Aug 2018 14:41:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3408C29FF6; Tue, 14 Aug 2018 14:41:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id ACF5A2A0DF for ; Tue, 14 Aug 2018 14:41:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 211F76E13D; Tue, 14 Aug 2018 14:41:14 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by gabe.freedesktop.org (Postfix) with ESMTPS id ED84A6E0B3 for ; Tue, 14 Aug 2018 14:41:10 +0000 (UTC) Received: by mail-wr1-x441.google.com with SMTP id r16-v6so17414002wrt.11 for ; Tue, 14 Aug 2018 07:41:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pD2v6ZtQTgrkUO26npEelNJNA+wlr4SHFuaDg7a2lDc=; b=eehUUu5WQ975INc+szrOZX7L8dYPxN95yzJZJoB6qBXSGrY61I4L7P1UnAC5ENy3oi yiBvMxbk52WsO5y7Rqpn0wViUJ1J3Y3XqnT5JSXPEEyv7kvUoXmlC0L0QKHTO+vJ35W8 yB+POl3CmvM1VhBi0WEKksSVI1iQfQZzHDOq4VNh1Db3sZkvcJaweY5tbRsLriylYdgM p6vBy2VZmb9O3RnUY3iY7gYaKGhbeLWcT29TqKp/ONfIQRQDXfvflJ6w/JtdromXPV97 m1M1yWX5i0ZnmJcJjl2ifMKTa3KsBxPXR0TvnFVf2oRSS/SaDrqlQ59hlCJEBgPhBOIl oHYQ== X-Gm-Message-State: AOUpUlEPJTFrCLlEr5iql7rEQYDuoyT3D5ASsVWEoLoJeuJah4rSSGg7 3txn1wutKN5kIzwyJxjU/HYfjqACl3o= X-Google-Smtp-Source: AA+uWPyLqo2UZTTpcRGUM3FG4hvE4ijD0hfdXeFfYhPY3cSlpJUu9HyuaJvSE+7kC7V4Mx3ogn+i4g== X-Received: by 2002:adf:b69c:: with SMTP id j28-v6mr13286423wre.200.1534257669431; Tue, 14 Aug 2018 07:41:09 -0700 (PDT) Received: from localhost.localdomain ([95.144.165.93]) by smtp.gmail.com with ESMTPSA id w17-v6sm8884719wmc.43.2018.08.14.07.41.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Aug 2018 07:41:08 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Tue, 14 Aug 2018 15:40:56 +0100 Message-Id: <20180814144058.19286-7-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180814144058.19286-1-tvrtko.ursulin@linux.intel.com> References: <20180814144058.19286-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH 6/8] drm/i915: Add global barrier support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Global barrier is a facility to allow serialization between different timelines. After calling i915_gem_set_global_barrier on a request, all following submissions on any engine will be set up as depending on this global barrier. Once the global barrier has been completed it automatically gets cleared and things continue as normal. This facility will be used by the upcoming context SSEU code. ------------------------------------------------------------------------- This code was part of the larger SSEU patch but I extracted it to be separate for ease of review and clarity. I think it originates from Chris Wilson so permission pending I will change the author and add appropriate S-o-B. ------------------------------------------------------------------------- Signed-off-by: Tvrtko Ursulin Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.h | 27 +++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_gem.c | 2 ++ drivers/gpu/drm/i915/i915_request.c | 16 ++++++++++++++++ 3 files changed, 45 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5c12d2676435..643089ba01b9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2098,6 +2098,16 @@ struct drm_i915_private { u32 active_requests; u32 request_serial; + /** + * Global barrier for the ability to serialize ordering between + * different timelines. + * + * Users can call i915_gem_set_global_barrier which will make + * all subsequent submission be execute only after this barrier + * has been completed. + */ + struct i915_gem_active global_barrier; + /** * Is the GPU currently considered idle, or busy executing * userspace requests? Whilst idle, we allow runtime power @@ -3230,6 +3240,23 @@ i915_vm_to_ppgtt(struct i915_address_space *vm) return container_of(vm, struct i915_hw_ppgtt, vm); } +/** + * i915_gem_set_global_barrier - orders submission on different timelines + * @i915: i915 device private + * @rq: request after which new submissions can proceed + * + * Sets the passed in request as the serialization point for all subsequent + * submissions, regardless of the engine/timeline. Subsequent requests will not + * be submitted to GPU until the global barrier has been completed. + */ +static inline void +i915_gem_set_global_barrier(struct drm_i915_private *i915, + struct i915_request *rq) +{ + lockdep_assert_held(&i915->drm.struct_mutex); + i915_gem_active_set(&i915->gt.global_barrier, rq); +} + /* i915_gem_fence_reg.c */ struct drm_i915_fence_reg * i915_reserve_fence(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 0453eb42a1a3..be462ef65786 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5752,6 +5752,8 @@ int i915_gem_init_early(struct drm_i915_private *dev_priv) if (!dev_priv->priorities) goto err_dependencies; + init_request_active(&dev_priv->gt.global_barrier, NULL); + INIT_LIST_HEAD(&dev_priv->gt.timelines); INIT_LIST_HEAD(&dev_priv->gt.active_rings); INIT_LIST_HEAD(&dev_priv->gt.closed_vma); diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 09ed48833b54..8b45f74dc748 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -644,6 +644,18 @@ submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) return NOTIFY_DONE; } +static int add_global_barrier(struct i915_request *rq) +{ + struct i915_request *barrier; + + barrier = i915_gem_active_raw(&rq->i915->gt.global_barrier, + &rq->i915->drm.struct_mutex); + if (barrier) + return i915_request_await_dma_fence(rq, &barrier->fence); + + return 0; +} + /** * i915_request_alloc - allocate a request structure * @@ -806,6 +818,10 @@ i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context *ctx) */ rq->head = rq->ring->emit; + ret = add_global_barrier(rq); + if (ret) + goto err_unwind; + /* Unconditionally invalidate GPU caches and TLBs. */ ret = engine->emit_flush(rq, EMIT_INVALIDATE); if (ret)