From patchwork Wed Aug 22 14:29:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10572981 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B9293112E for ; Wed, 22 Aug 2018 14:29:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A9A442B3D3 for ; Wed, 22 Aug 2018 14:29:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9C52E2B64A; Wed, 22 Aug 2018 14:29:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4932A2B3D3 for ; Wed, 22 Aug 2018 14:29:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6B8886E212; Wed, 22 Aug 2018 14:29:36 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by gabe.freedesktop.org (Postfix) with ESMTPS id BA52E89DFF for ; Wed, 22 Aug 2018 14:29:34 +0000 (UTC) Received: by mail-wr1-x444.google.com with SMTP id v16-v6so1778977wro.11 for ; Wed, 22 Aug 2018 07:29:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=yWzKPqbUNz/JuAMj2b5OZxAwsdgmSqaVAjYDWchtzKg=; b=c2+oQYdZjcz6Or61TR2vyOWtCKnUeN/eTlKmpLj4bRR7gcdwdpGWVwM8lc2rSCajPA 3G3lRRGHNLVs6UdBYgJONw1GA/aqtjQDK00fCVhB69oqjt0Dy387My+UcQ4RvxqM8gE/ HG26Z2J5fFVjyVFrrGZC1DtLyXdMuEC9EewAN/dCrqawOlUqhsPTMf/xXjhiuMVljfR0 AeeUmiN3HgIcDcsto5YFifIKGjf/9a4hFrg4MRhLyQpmDXw+XTzflu9JgnUSlSAb9j6g KJOxEYsK3PD8RKbfXp6ikpEJ9q90kIeyFxstS2a5bddoHh4JslH/8Tk3fiwRHpNfyXgy zITg== X-Gm-Message-State: APzg51Asg+Dgm3waRLw6uwB2IGLWUbzs7SU2p+tigWGJThoZ/T5+huI2 1jCqhv5NPQrU10K4+Uo1q6UWNFfOEuU= X-Google-Smtp-Source: ANB0VdZnojcuYBDdyvBOMFq9Ao8uoWA3ddxIYTWQ+qdHUQ1en0N/lpcLlgmp6aWIJ4J9ewX5PoQJRQ== X-Received: by 2002:adf:a936:: with SMTP id u51-v6mr15516910wrc.175.1534948173026; Wed, 22 Aug 2018 07:29:33 -0700 (PDT) Received: from localhost.localdomain ([95.144.165.37]) by smtp.gmail.com with ESMTPSA id z184-v6sm533470wmz.0.2018.08.22.07.29.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 22 Aug 2018 07:29:32 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Wed, 22 Aug 2018 15:29:27 +0100 Message-Id: <20180822142927.19565-1-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 Subject: [Intel-gfx] [PATCH] drm/i915: Fix subslice configuration on Gen9LP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin According to the documentation, when programming the subslice count power- gating configuration register, the value to be written into it on Gen9LP should actually in the format of: 1 slice = 0x001 2 slices = 0x010 3 slices = 0x100 And not the popcount of the enabled subslice mask as on other platforms. So on Gen9LP platforms we have been programming 0x11 into those bits, but the documentation does not explain what would that achieve. Could it be that we enable only two subslice on three sub-slice parts? Or hardware simply ignores it and sticks with the maximum configuration? Signed-off-by: Tvrtko Ursulin Cc: Lionel Landwerlin Bspec: 12247 Reviewed-by: Lionel Landwerlin --- Could this actually be true or I am severely misreading the docs? It does not sound plausible to me this would have been missed all this time.. How to test in what configuration do these parts run before and after this patch? --- drivers/gpu/drm/i915/intel_lrc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 36050f085071..cdfa962a1975 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2508,9 +2508,15 @@ make_rpcs(struct drm_i915_private *dev_priv) } if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) { + u8 val; + + val = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]); + + if (IS_GEN9_LP(dev_priv)) + val = BIT(val - 1); + rpcs |= GEN8_RPCS_SS_CNT_ENABLE; - rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]) << - GEN8_RPCS_SS_CNT_SHIFT; + rpcs |= val << GEN8_RPCS_SS_CNT_SHIFT; rpcs |= GEN8_RPCS_ENABLE; }