From patchwork Wed Aug 22 16:18:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10573045 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8593813B6 for ; Wed, 22 Aug 2018 16:18:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7311F2B4CE for ; Wed, 22 Aug 2018 16:18:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6663C2B4E3; Wed, 22 Aug 2018 16:18:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 093E22B4CE for ; Wed, 22 Aug 2018 16:18:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1C6FF6E395; Wed, 22 Aug 2018 16:18:13 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4A9D66E395 for ; Wed, 22 Aug 2018 16:18:12 +0000 (UTC) Received: by mail-wm0-x244.google.com with SMTP id y2-v6so2560713wma.1 for ; Wed, 22 Aug 2018 09:18:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=1J8QQUpLT5SqfFxhRRq1x95lZLT+lOee1Z7LiKeRYo8=; b=ei19Ir93yMlrrB1cdmC8MZCPEXvCCi2+GLxmJd2hhf4fQzAWlzRXBONTsfeXQEmTNq vS0VOGQJC3/QPQMnEk1UBNrhHSbrNv3Zx0Lm8rkbJ9CRRUFFqL7DOGabklEgdw6WYIr9 S9Nr9GJfFEGfybnDgOuXilqRsAqRKGX8ocUwfmFkblpgXnDHoXYvxoEPZKhZMW4ftBRm Y6O/Jwqr1JB6Q3rvXI7Vc1uHGKloUvt/3mibdJB8D9ma2+4/6BJ/5IdgbdtNGnmD4l5B oUpJRS9SYnuLmSKf8CjQ1WtdzAUaV70wXJgLdqPUGTGjyKZmXe/yP3w57Qiu9td9WC2b PxxA== X-Gm-Message-State: APzg51CCGbK6Iyp/VkGR8Hn07wQGgB9OwhFGXL3n9tWS1vGMcIXnbRC2 RjTn1ZOXKRqhL81qdrLnGxH5v+A9z3c= X-Google-Smtp-Source: ANB0VdaFBZDK2e8swrrW/oNjRGwe0Hpmz3c3fgfCWYD+A9Wn/+YBlkh/YQJKwqJfW4/nwz86nkX/sw== X-Received: by 2002:a1c:3314:: with SMTP id z20-v6mr2650247wmz.95.1534954690809; Wed, 22 Aug 2018 09:18:10 -0700 (PDT) Received: from localhost.localdomain ([95.144.165.37]) by smtp.gmail.com with ESMTPSA id 60-v6sm3732731wre.82.2018.08.22.09.18.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 22 Aug 2018 09:18:10 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Wed, 22 Aug 2018 17:18:05 +0100 Message-Id: <20180822161805.7105-1-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 Subject: [Intel-gfx] [PATCH] drm/i915/icl: Fix context slice count configuration X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Bitfield width for configuring the active slice count has grown in Gen11 so we need to program the GEN8_R_PWR_CLK_STATE accordingly. Current code was always requesting eight times the number of slices (due writting to a bitfield starting three bits higher than it should). These requests were luckily a) capped by the hardware to the available number of slices, and b) we haven't yet exported the code to ask for reduced slice configurations. Due both of the above there was no impact from this incorrect programming but we should still fix it. Signed-off-by: Tvrtko Ursulin Bspec: 12247 Reported-by: tony.ye@intel.com Suggested-by: Lionel Landwerlin Cc: Lionel Landwerlin Cc: tony.ye@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_lrc.c | 12 ++++++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 59d06d0055bb..640f7b774a26 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -344,6 +344,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GEN8_RPCS_S_CNT_ENABLE (1 << 18) #define GEN8_RPCS_S_CNT_SHIFT 15 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) +#define GEN11_RPCS_S_CNT_SHIFT 12 +#define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT) #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) #define GEN8_RPCS_SS_CNT_SHIFT 8 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 36050f085071..43b8b0675ba0 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2501,10 +2501,14 @@ make_rpcs(struct drm_i915_private *dev_priv) * enablement. */ if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { - rpcs |= GEN8_RPCS_S_CNT_ENABLE; - rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) << - GEN8_RPCS_S_CNT_SHIFT; - rpcs |= GEN8_RPCS_ENABLE; + rpcs = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask); + + if (INTEL_GEN(dev_priv) >= 11) + rpcs <<= GEN11_RPCS_S_CNT_SHIFT; + else + rpcs <<= GEN8_RPCS_S_CNT_SHIFT; + + rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_S_CNT_ENABLE; } if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {