| Message ID | 20180829191056.63760-5-michal.wajdeczko@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | New GuC ABI | expand |
On Wed, 2018-08-29 at 12:10 -0700, Wajdeczko, Michal wrote: > Gen11 GuC boot parameter definitions are different than previously > used for Gen9. Try to support both definitions until new firmwares > for pre-Gen11 will be available. > > Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Michel Thierry <michel.thierry@intel.com> > Cc: John Spotswood <john.a.spotswood@intel.com> > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > Cc: Tony Ye <tony.ye@intel.com> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > Cc: Jeff Mcgee <jeff.mcgee@intel.com> > Cc: Antonio Argenziano <antonio.argenziano@intel.com> > Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com> Reviewed-by: John Spotswood <john.a.spotswood@intel.com> > --- > drivers/gpu/drm/i915/intel_guc.c | 76 > +++++++++++++++++++++++++---------- > drivers/gpu/drm/i915/intel_guc_fwif.h | 59 +++++++++++++---------- > ---- > 2 files changed, 83 insertions(+), 52 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_guc.c > b/drivers/gpu/drm/i915/intel_guc.c > index 982bcc8..a9c2f7b 100644 > --- a/drivers/gpu/drm/i915/intel_guc.c > +++ b/drivers/gpu/drm/i915/intel_guc.c > @@ -230,14 +230,7 @@ void intel_guc_fini(struct intel_guc *guc) > static u32 guc_ctl_debug_flags(struct intel_guc *guc) > { > u32 level = intel_guc_log_get_level(&guc->log); > - u32 flags; > - u32 ads; > - > - ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> > PAGE_SHIFT; > - flags = ads << GUC_ADS_ADDR_SHIFT | GUC_ADS_ENABLED; > - > - if (!GUC_LOG_LEVEL_IS_ENABLED(level)) > - flags |= GUC_LOG_DEFAULT_DISABLED; > + u32 flags = 0; > > if (!GUC_LOG_LEVEL_IS_VERBOSE(level)) > flags |= GUC_LOG_DISABLED; > @@ -248,20 +241,28 @@ static u32 guc_ctl_debug_flags(struct intel_guc > *guc) > return flags; > } > > -static u32 guc_ctl_feature_flags(struct intel_guc *guc) > +static u32 guc9_ctl_debug_flags(struct intel_guc *guc) > { > - u32 flags = 0; > + u32 level = intel_guc_log_get_level(&guc->log); > + u32 flags; > + u32 ads; > > - flags |= GUC_CTL_VCS2_ENABLED; > + ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> > PAGE_SHIFT; > + flags = ads << GUC9_ADS_ADDR_SHIFT | GUC9_ADS_ENABLED; > > - if (USES_GUC_SUBMISSION(guc_to_i915(guc))) > - flags |= GUC_CTL_KERNEL_SUBMISSIONS; > - else > - flags |= GUC_CTL_DISABLE_SCHEDULER; > + if (!GUC_LOG_LEVEL_IS_ENABLED(level)) > + flags |= GUC9_LOG_DEFAULT_DISABLED; > + > + flags |= guc_ctl_debug_flags(guc); > > return flags; > } > > +static u32 guc9_ctl_feature_flags(struct intel_guc *guc) > +{ > + return GUC9_CTL_VCS2_ENABLED | GUC9_CTL_DISABLE_SCHEDULER; > +} > + > static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc) > { > u32 flags = 0; > @@ -279,6 +280,16 @@ static u32 guc_ctl_ctxinfo_flags(struct > intel_guc *guc) > return flags; > } > > +static u32 guc_ctl_feature_flags(struct intel_guc *guc) > +{ > + u32 flags = 0; > + > + if (!USES_GUC_SUBMISSION(guc_to_i915(guc))) > + flags |= GUC_CTL_DISABLE_SCHEDULER; > + > + return flags; > +} > + > static u32 guc_ctl_log_params_flags(struct intel_guc *guc) > { > u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> > PAGE_SHIFT; > @@ -320,22 +331,39 @@ static u32 guc_ctl_log_params_flags(struct > intel_guc *guc) > return flags; > } > > -static void guc_prepare_params(struct intel_guc *guc, u32 *params) > +static void guc9_prepare_params(struct intel_guc *guc, u32 *params) > { > /* > * GuC ARAT increment is 10 ns. GuC default scheduler > quantum is one > * second. This ARAR is calculated by: > * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = > 1000000000 / 10 > */ > - params[GUC_CTL_ARAT_HIGH] = 0; > - params[GUC_CTL_ARAT_LOW] = 100000000; > + params[GUC9_CTL_ARAT_HIGH] = 0; > + params[GUC9_CTL_ARAT_LOW] = 100000000; > + > + params[GUC9_CTL_WA] |= GUC9_CTL_WA_UK_BY_DRIVER; > > - params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER; > + params[GUC9_CTL_FEATURE] = guc9_ctl_feature_flags(guc); > + params[GUC9_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); > + params[GUC9_CTL_DEBUG] = guc9_ctl_debug_flags(guc); > + params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc); > +} > > +static u32 guc_ctl_ads_flags(struct intel_guc *guc) > +{ > + u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> > PAGE_SHIFT; > + u32 flags = ads << GUC_ADS_ADDR_SHIFT; > + > + return flags; > +} > + > +static void guc11_prepare_params(struct intel_guc *guc, u32 *params) > +{ > + params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc); > + params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); > params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); > - params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); > params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); > - params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc); > + params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); > } > > static void guc_write_params(struct intel_guc *guc, const u32 > *params) > @@ -367,10 +395,14 @@ static void guc_write_params(struct intel_guc > *guc, const u32 *params) > */ > void intel_guc_init_params(struct intel_guc *guc) > { > + struct drm_i915_private *i915 = guc_to_i915(guc); > u32 params[GUC_CTL_MAX_DWORDS]; > > memset(params, 0, sizeof(params)); > - guc_prepare_params(guc, params); > + if (INTEL_GEN(i915) >= 11) > + guc11_prepare_params(guc, params); > + else > + guc9_prepare_params(guc, params); > guc_write_params(guc, params); > } > > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h > b/drivers/gpu/drm/i915/intel_guc_fwif.h > index 8382d59..7070e36 100644 > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h > @@ -71,44 +71,28 @@ > #define GUC_STAGE_DESC_ATTR_PCH BIT(6) > #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) > > -/* The guc control data is 10 DWORDs */ > +/* New GuC control data */ > #define GUC_CTL_CTXINFO 0 > #define GUC_CTL_CTXNUM_IN16_SHIFT 0 > #define GUC_CTL_BASE_ADDR_SHIFT 12 > > -#define GUC_CTL_ARAT_HIGH 1 > -#define GUC_CTL_ARAT_LOW 2 > - > -#define GUC_CTL_DEVICE_INFO 3 > - > -#define GUC_CTL_LOG_PARAMS 4 > +#define GUC_CTL_LOG_PARAMS 1 > #define GUC_LOG_VALID (1 << 0) > #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) > #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) > #define GUC_LOG_CRASH_SHIFT 4 > -#define GUC_LOG_CRASH_MASK (0x1 << > GUC_LOG_CRASH_SHIFT) > +#define GUC_LOG_CRASH_MASK (0x3 << > GUC_LOG_CRASH_SHIFT) > #define GUC_LOG_DPC_SHIFT 6 > #define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT) > #define GUC_LOG_ISR_SHIFT 9 > #define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT) > #define GUC_LOG_BUF_ADDR_SHIFT 12 > > -#define GUC_CTL_PAGE_FAULT_CONTROL 5 > - > -#define GUC_CTL_WA 6 > -#define GUC_CTL_WA_UK_BY_DRIVER (1 << 3) > +#define GUC_CTL_WA 2 > +#define GUC_CTL_FEATURE 3 > +#define GUC_CTL_DISABLE_SCHEDULER (1 << 14) > > -#define GUC_CTL_FEATURE 7 > -#define GUC_CTL_VCS2_ENABLED (1 << 0) > -#define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1) > -#define GUC_CTL_FEATURE2 (1 << 2) > -#define GUC_CTL_POWER_GATING (1 << 3) > -#define GUC_CTL_DISABLE_SCHEDULER (1 << 4) > -#define GUC_CTL_PREEMPTION_LOG (1 << 5) > -#define GUC_CTL_ENABLE_SLPC (1 << 7) > -#define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8) > - > -#define GUC_CTL_DEBUG 8 > +#define GUC_CTL_DEBUG 4 > #define GUC_LOG_VERBOSITY_SHIFT 0 > #define GUC_LOG_VERBOSITY_LOW (0 << > GUC_LOG_VERBOSITY_SHIFT) > #define GUC_LOG_VERBOSITY_MED (1 << > GUC_LOG_VERBOSITY_SHIFT) > @@ -121,13 +105,28 @@ > #define GUC_LOG_DESTINATION_MASK (3 << 4) > #define GUC_LOG_DISABLED (1 << 6) > #define GUC_PROFILE_ENABLED (1 << 7) > -#define GUC_WQ_TRACK_ENABLED (1 << 8) > -#define GUC_ADS_ENABLED (1 << 9) > -#define GUC_LOG_DEFAULT_DISABLED (1 << 10) > -#define GUC_ADS_ADDR_SHIFT 11 > -#define GUC_ADS_ADDR_MASK 0xfffff800 > - > -#define GUC_CTL_RSRVD 9 > +#define GUC9_WQ_TRACK_ENABLED (1 << 8) > +#define GUC9_ADS_ENABLED (1 << 9) > +#define GUC9_LOG_DEFAULT_DISABLED (1 << 10) > +#define GUC9_ADS_ADDR_SHIFT 11 > +#define GUC9_ADS_ADDR_MASK 0xfffff800 > + > +#define GUC_CTL_ADS 5 > +#define GUC_ADS_ADDR_SHIFT 1 > +#define GUC_ADS_ADDR_MASK (0xFFFFF << > GUC_ADS_ADDR_SHIFT) > + > +/* Legacy GuC control data */ > +#define GUC9_CTL_ARAT_HIGH 1 > +#define GUC9_CTL_ARAT_LOW 2 > +#define GUC9_CTL_DEVICE_INFO 3 > +#define GUC9_CTL_LOG_PARAMS 4 > +#define GUC9_CTL_PAGE_FAULT_CONTROL 5 > +#define GUC9_CTL_WA 6 > +#define GUC9_CTL_WA_UK_BY_DRIVER (1 << 3) > +#define GUC9_CTL_FEATURE 7 > +#define GUC9_CTL_VCS2_ENABLED (1 << 0) > +#define GUC9_CTL_DISABLE_SCHEDULER (1 << 4) > +#define GUC9_CTL_DEBUG 8 > > #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) > /* [1..14] */ >
Quoting Michal Wajdeczko (2018-08-29 22:10:38) > Gen11 GuC boot parameter definitions are different than previously > used for Gen9. Try to support both definitions until new firmwares > for pre-Gen11 will be available. This is exactly the kind of branching we want to avoid. Purpose of the GuC is to hide per-Gen differences, not to cause them :) The new interface code should just be GuC interface code (not refer to ICL or any generation specifically), then pre-Gen11 platforms just won't have a drm-tip compatible firmware until -- well -- they do have it. So for the series, just axe the old interface and replace it in-place. Makes the review of the interface differences much more effective, too. Regards, Joonas
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 982bcc8..a9c2f7b 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -230,14 +230,7 @@ void intel_guc_fini(struct intel_guc *guc) static u32 guc_ctl_debug_flags(struct intel_guc *guc) { u32 level = intel_guc_log_get_level(&guc->log); - u32 flags; - u32 ads; - - ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT; - flags = ads << GUC_ADS_ADDR_SHIFT | GUC_ADS_ENABLED; - - if (!GUC_LOG_LEVEL_IS_ENABLED(level)) - flags |= GUC_LOG_DEFAULT_DISABLED; + u32 flags = 0; if (!GUC_LOG_LEVEL_IS_VERBOSE(level)) flags |= GUC_LOG_DISABLED; @@ -248,20 +241,28 @@ static u32 guc_ctl_debug_flags(struct intel_guc *guc) return flags; } -static u32 guc_ctl_feature_flags(struct intel_guc *guc) +static u32 guc9_ctl_debug_flags(struct intel_guc *guc) { - u32 flags = 0; + u32 level = intel_guc_log_get_level(&guc->log); + u32 flags; + u32 ads; - flags |= GUC_CTL_VCS2_ENABLED; + ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT; + flags = ads << GUC9_ADS_ADDR_SHIFT | GUC9_ADS_ENABLED; - if (USES_GUC_SUBMISSION(guc_to_i915(guc))) - flags |= GUC_CTL_KERNEL_SUBMISSIONS; - else - flags |= GUC_CTL_DISABLE_SCHEDULER; + if (!GUC_LOG_LEVEL_IS_ENABLED(level)) + flags |= GUC9_LOG_DEFAULT_DISABLED; + + flags |= guc_ctl_debug_flags(guc); return flags; } +static u32 guc9_ctl_feature_flags(struct intel_guc *guc) +{ + return GUC9_CTL_VCS2_ENABLED | GUC9_CTL_DISABLE_SCHEDULER; +} + static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc) { u32 flags = 0; @@ -279,6 +280,16 @@ static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc) return flags; } +static u32 guc_ctl_feature_flags(struct intel_guc *guc) +{ + u32 flags = 0; + + if (!USES_GUC_SUBMISSION(guc_to_i915(guc))) + flags |= GUC_CTL_DISABLE_SCHEDULER; + + return flags; +} + static u32 guc_ctl_log_params_flags(struct intel_guc *guc) { u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT; @@ -320,22 +331,39 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc) return flags; } -static void guc_prepare_params(struct intel_guc *guc, u32 *params) +static void guc9_prepare_params(struct intel_guc *guc, u32 *params) { /* * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one * second. This ARAR is calculated by: * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10 */ - params[GUC_CTL_ARAT_HIGH] = 0; - params[GUC_CTL_ARAT_LOW] = 100000000; + params[GUC9_CTL_ARAT_HIGH] = 0; + params[GUC9_CTL_ARAT_LOW] = 100000000; + + params[GUC9_CTL_WA] |= GUC9_CTL_WA_UK_BY_DRIVER; - params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER; + params[GUC9_CTL_FEATURE] = guc9_ctl_feature_flags(guc); + params[GUC9_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); + params[GUC9_CTL_DEBUG] = guc9_ctl_debug_flags(guc); + params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc); +} +static u32 guc_ctl_ads_flags(struct intel_guc *guc) +{ + u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT; + u32 flags = ads << GUC_ADS_ADDR_SHIFT; + + return flags; +} + +static void guc11_prepare_params(struct intel_guc *guc, u32 *params) +{ + params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc); + params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); - params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); - params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc); + params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); } static void guc_write_params(struct intel_guc *guc, const u32 *params) @@ -367,10 +395,14 @@ static void guc_write_params(struct intel_guc *guc, const u32 *params) */ void intel_guc_init_params(struct intel_guc *guc) { + struct drm_i915_private *i915 = guc_to_i915(guc); u32 params[GUC_CTL_MAX_DWORDS]; memset(params, 0, sizeof(params)); - guc_prepare_params(guc, params); + if (INTEL_GEN(i915) >= 11) + guc11_prepare_params(guc, params); + else + guc9_prepare_params(guc, params); guc_write_params(guc, params); } diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 8382d59..7070e36 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -71,44 +71,28 @@ #define GUC_STAGE_DESC_ATTR_PCH BIT(6) #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) -/* The guc control data is 10 DWORDs */ +/* New GuC control data */ #define GUC_CTL_CTXINFO 0 #define GUC_CTL_CTXNUM_IN16_SHIFT 0 #define GUC_CTL_BASE_ADDR_SHIFT 12 -#define GUC_CTL_ARAT_HIGH 1 -#define GUC_CTL_ARAT_LOW 2 - -#define GUC_CTL_DEVICE_INFO 3 - -#define GUC_CTL_LOG_PARAMS 4 +#define GUC_CTL_LOG_PARAMS 1 #define GUC_LOG_VALID (1 << 0) #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) #define GUC_LOG_CRASH_SHIFT 4 -#define GUC_LOG_CRASH_MASK (0x1 << GUC_LOG_CRASH_SHIFT) +#define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT) #define GUC_LOG_DPC_SHIFT 6 #define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT) #define GUC_LOG_ISR_SHIFT 9 #define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT) #define GUC_LOG_BUF_ADDR_SHIFT 12 -#define GUC_CTL_PAGE_FAULT_CONTROL 5 - -#define GUC_CTL_WA 6 -#define GUC_CTL_WA_UK_BY_DRIVER (1 << 3) +#define GUC_CTL_WA 2 +#define GUC_CTL_FEATURE 3 +#define GUC_CTL_DISABLE_SCHEDULER (1 << 14) -#define GUC_CTL_FEATURE 7 -#define GUC_CTL_VCS2_ENABLED (1 << 0) -#define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1) -#define GUC_CTL_FEATURE2 (1 << 2) -#define GUC_CTL_POWER_GATING (1 << 3) -#define GUC_CTL_DISABLE_SCHEDULER (1 << 4) -#define GUC_CTL_PREEMPTION_LOG (1 << 5) -#define GUC_CTL_ENABLE_SLPC (1 << 7) -#define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8) - -#define GUC_CTL_DEBUG 8 +#define GUC_CTL_DEBUG 4 #define GUC_LOG_VERBOSITY_SHIFT 0 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) @@ -121,13 +105,28 @@ #define GUC_LOG_DESTINATION_MASK (3 << 4) #define GUC_LOG_DISABLED (1 << 6) #define GUC_PROFILE_ENABLED (1 << 7) -#define GUC_WQ_TRACK_ENABLED (1 << 8) -#define GUC_ADS_ENABLED (1 << 9) -#define GUC_LOG_DEFAULT_DISABLED (1 << 10) -#define GUC_ADS_ADDR_SHIFT 11 -#define GUC_ADS_ADDR_MASK 0xfffff800 - -#define GUC_CTL_RSRVD 9 +#define GUC9_WQ_TRACK_ENABLED (1 << 8) +#define GUC9_ADS_ENABLED (1 << 9) +#define GUC9_LOG_DEFAULT_DISABLED (1 << 10) +#define GUC9_ADS_ADDR_SHIFT 11 +#define GUC9_ADS_ADDR_MASK 0xfffff800 + +#define GUC_CTL_ADS 5 +#define GUC_ADS_ADDR_SHIFT 1 +#define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT) + +/* Legacy GuC control data */ +#define GUC9_CTL_ARAT_HIGH 1 +#define GUC9_CTL_ARAT_LOW 2 +#define GUC9_CTL_DEVICE_INFO 3 +#define GUC9_CTL_LOG_PARAMS 4 +#define GUC9_CTL_PAGE_FAULT_CONTROL 5 +#define GUC9_CTL_WA 6 +#define GUC9_CTL_WA_UK_BY_DRIVER (1 << 3) +#define GUC9_CTL_FEATURE 7 +#define GUC9_CTL_VCS2_ENABLED (1 << 0) +#define GUC9_CTL_DISABLE_SCHEDULER (1 << 4) +#define GUC9_CTL_DEBUG 8 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
Gen11 GuC boot parameter definitions are different than previously used for Gen9. Try to support both definitions until new firmwares for pre-Gen11 will be available. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: John Spotswood <john.a.spotswood@intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Cc: Tony Ye <tony.ye@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Jeff Mcgee <jeff.mcgee@intel.com> Cc: Antonio Argenziano <antonio.argenziano@intel.com> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com> --- drivers/gpu/drm/i915/intel_guc.c | 76 +++++++++++++++++++++++++---------- drivers/gpu/drm/i915/intel_guc_fwif.h | 59 +++++++++++++-------------- 2 files changed, 83 insertions(+), 52 deletions(-)