From patchwork Wed Aug 29 19:10:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10580777 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CDB10174A for ; Wed, 29 Aug 2018 19:13:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BEAB828179 for ; Wed, 29 Aug 2018 19:13:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B2B9428396; Wed, 29 Aug 2018 19:13:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2524628179 for ; Wed, 29 Aug 2018 19:13:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 813F66E58D; Wed, 29 Aug 2018 19:13:03 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id E1C0D6E58D for ; Wed, 29 Aug 2018 19:13:02 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Aug 2018 12:13:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,304,1531810800"; d="scan'208";a="68852882" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga007.jf.intel.com with ESMTP; 29 Aug 2018 12:11:19 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [172.28.181.6]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id w7TJB9RK021381; Wed, 29 Aug 2018 20:11:18 +0100 From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Wed, 29 Aug 2018 19:10:38 +0000 Message-Id: <20180829191056.63760-5-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20180829191056.63760-1-michal.wajdeczko@intel.com> References: <20180829191056.63760-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 04/21] drm/i915/guc: Support dual Gen9/Gen11 parameters block X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rodrigo Vivi , Sujaritha Sundaresan MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Gen11 GuC boot parameter definitions are different than previously used for Gen9. Try to support both definitions until new firmwares for pre-Gen11 will be available. Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Rodrigo Vivi Cc: Daniele Ceraolo Spurio Cc: Michel Thierry Cc: John Spotswood Cc: Vinay Belgaumkar Cc: Tony Ye Cc: Anusha Srivatsa Cc: Jeff Mcgee Cc: Antonio Argenziano Cc: Sujaritha Sundaresan Reviewed-by: John Spotswood --- drivers/gpu/drm/i915/intel_guc.c | 76 +++++++++++++++++++++++++---------- drivers/gpu/drm/i915/intel_guc_fwif.h | 59 +++++++++++++-------------- 2 files changed, 83 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 982bcc8..a9c2f7b 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -230,14 +230,7 @@ void intel_guc_fini(struct intel_guc *guc) static u32 guc_ctl_debug_flags(struct intel_guc *guc) { u32 level = intel_guc_log_get_level(&guc->log); - u32 flags; - u32 ads; - - ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT; - flags = ads << GUC_ADS_ADDR_SHIFT | GUC_ADS_ENABLED; - - if (!GUC_LOG_LEVEL_IS_ENABLED(level)) - flags |= GUC_LOG_DEFAULT_DISABLED; + u32 flags = 0; if (!GUC_LOG_LEVEL_IS_VERBOSE(level)) flags |= GUC_LOG_DISABLED; @@ -248,20 +241,28 @@ static u32 guc_ctl_debug_flags(struct intel_guc *guc) return flags; } -static u32 guc_ctl_feature_flags(struct intel_guc *guc) +static u32 guc9_ctl_debug_flags(struct intel_guc *guc) { - u32 flags = 0; + u32 level = intel_guc_log_get_level(&guc->log); + u32 flags; + u32 ads; - flags |= GUC_CTL_VCS2_ENABLED; + ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT; + flags = ads << GUC9_ADS_ADDR_SHIFT | GUC9_ADS_ENABLED; - if (USES_GUC_SUBMISSION(guc_to_i915(guc))) - flags |= GUC_CTL_KERNEL_SUBMISSIONS; - else - flags |= GUC_CTL_DISABLE_SCHEDULER; + if (!GUC_LOG_LEVEL_IS_ENABLED(level)) + flags |= GUC9_LOG_DEFAULT_DISABLED; + + flags |= guc_ctl_debug_flags(guc); return flags; } +static u32 guc9_ctl_feature_flags(struct intel_guc *guc) +{ + return GUC9_CTL_VCS2_ENABLED | GUC9_CTL_DISABLE_SCHEDULER; +} + static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc) { u32 flags = 0; @@ -279,6 +280,16 @@ static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc) return flags; } +static u32 guc_ctl_feature_flags(struct intel_guc *guc) +{ + u32 flags = 0; + + if (!USES_GUC_SUBMISSION(guc_to_i915(guc))) + flags |= GUC_CTL_DISABLE_SCHEDULER; + + return flags; +} + static u32 guc_ctl_log_params_flags(struct intel_guc *guc) { u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT; @@ -320,22 +331,39 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc) return flags; } -static void guc_prepare_params(struct intel_guc *guc, u32 *params) +static void guc9_prepare_params(struct intel_guc *guc, u32 *params) { /* * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one * second. This ARAR is calculated by: * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10 */ - params[GUC_CTL_ARAT_HIGH] = 0; - params[GUC_CTL_ARAT_LOW] = 100000000; + params[GUC9_CTL_ARAT_HIGH] = 0; + params[GUC9_CTL_ARAT_LOW] = 100000000; + + params[GUC9_CTL_WA] |= GUC9_CTL_WA_UK_BY_DRIVER; - params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER; + params[GUC9_CTL_FEATURE] = guc9_ctl_feature_flags(guc); + params[GUC9_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); + params[GUC9_CTL_DEBUG] = guc9_ctl_debug_flags(guc); + params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc); +} +static u32 guc_ctl_ads_flags(struct intel_guc *guc) +{ + u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT; + u32 flags = ads << GUC_ADS_ADDR_SHIFT; + + return flags; +} + +static void guc11_prepare_params(struct intel_guc *guc, u32 *params) +{ + params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc); + params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); - params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); - params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc); + params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); } static void guc_write_params(struct intel_guc *guc, const u32 *params) @@ -367,10 +395,14 @@ static void guc_write_params(struct intel_guc *guc, const u32 *params) */ void intel_guc_init_params(struct intel_guc *guc) { + struct drm_i915_private *i915 = guc_to_i915(guc); u32 params[GUC_CTL_MAX_DWORDS]; memset(params, 0, sizeof(params)); - guc_prepare_params(guc, params); + if (INTEL_GEN(i915) >= 11) + guc11_prepare_params(guc, params); + else + guc9_prepare_params(guc, params); guc_write_params(guc, params); } diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 8382d59..7070e36 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -71,44 +71,28 @@ #define GUC_STAGE_DESC_ATTR_PCH BIT(6) #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) -/* The guc control data is 10 DWORDs */ +/* New GuC control data */ #define GUC_CTL_CTXINFO 0 #define GUC_CTL_CTXNUM_IN16_SHIFT 0 #define GUC_CTL_BASE_ADDR_SHIFT 12 -#define GUC_CTL_ARAT_HIGH 1 -#define GUC_CTL_ARAT_LOW 2 - -#define GUC_CTL_DEVICE_INFO 3 - -#define GUC_CTL_LOG_PARAMS 4 +#define GUC_CTL_LOG_PARAMS 1 #define GUC_LOG_VALID (1 << 0) #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) #define GUC_LOG_CRASH_SHIFT 4 -#define GUC_LOG_CRASH_MASK (0x1 << GUC_LOG_CRASH_SHIFT) +#define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT) #define GUC_LOG_DPC_SHIFT 6 #define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT) #define GUC_LOG_ISR_SHIFT 9 #define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT) #define GUC_LOG_BUF_ADDR_SHIFT 12 -#define GUC_CTL_PAGE_FAULT_CONTROL 5 - -#define GUC_CTL_WA 6 -#define GUC_CTL_WA_UK_BY_DRIVER (1 << 3) +#define GUC_CTL_WA 2 +#define GUC_CTL_FEATURE 3 +#define GUC_CTL_DISABLE_SCHEDULER (1 << 14) -#define GUC_CTL_FEATURE 7 -#define GUC_CTL_VCS2_ENABLED (1 << 0) -#define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1) -#define GUC_CTL_FEATURE2 (1 << 2) -#define GUC_CTL_POWER_GATING (1 << 3) -#define GUC_CTL_DISABLE_SCHEDULER (1 << 4) -#define GUC_CTL_PREEMPTION_LOG (1 << 5) -#define GUC_CTL_ENABLE_SLPC (1 << 7) -#define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8) - -#define GUC_CTL_DEBUG 8 +#define GUC_CTL_DEBUG 4 #define GUC_LOG_VERBOSITY_SHIFT 0 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) @@ -121,13 +105,28 @@ #define GUC_LOG_DESTINATION_MASK (3 << 4) #define GUC_LOG_DISABLED (1 << 6) #define GUC_PROFILE_ENABLED (1 << 7) -#define GUC_WQ_TRACK_ENABLED (1 << 8) -#define GUC_ADS_ENABLED (1 << 9) -#define GUC_LOG_DEFAULT_DISABLED (1 << 10) -#define GUC_ADS_ADDR_SHIFT 11 -#define GUC_ADS_ADDR_MASK 0xfffff800 - -#define GUC_CTL_RSRVD 9 +#define GUC9_WQ_TRACK_ENABLED (1 << 8) +#define GUC9_ADS_ENABLED (1 << 9) +#define GUC9_LOG_DEFAULT_DISABLED (1 << 10) +#define GUC9_ADS_ADDR_SHIFT 11 +#define GUC9_ADS_ADDR_MASK 0xfffff800 + +#define GUC_CTL_ADS 5 +#define GUC_ADS_ADDR_SHIFT 1 +#define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT) + +/* Legacy GuC control data */ +#define GUC9_CTL_ARAT_HIGH 1 +#define GUC9_CTL_ARAT_LOW 2 +#define GUC9_CTL_DEVICE_INFO 3 +#define GUC9_CTL_LOG_PARAMS 4 +#define GUC9_CTL_PAGE_FAULT_CONTROL 5 +#define GUC9_CTL_WA 6 +#define GUC9_CTL_WA_UK_BY_DRIVER (1 << 3) +#define GUC9_CTL_FEATURE 7 +#define GUC9_CTL_VCS2_ENABLED (1 << 0) +#define GUC9_CTL_DISABLE_SCHEDULER (1 << 4) +#define GUC9_CTL_DEBUG 8 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */