@@ -1881,6 +1881,17 @@ struct drm_i915_private {
#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
#define GEN11_MAX_CONTEXT_HW_ID (1 << 11) /* exclusive */
#define GEN11_MAX_CONTEXT_HW_ID_WITH_GUC (GEN11_MAX_CONTEXT_HW_ID - 16)
+
+ /*
+ * Hooks for context (per-engine context, not gem context)
+ * allocation, deallocation and descriptor update.
+ */
+ void (*alloc_hook)(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine);
+ void (*update_hook)(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine);
+ void (*free_hook)(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine);
} contexts;
u32 fdi_rx_config;
@@ -126,9 +126,13 @@ static void i915_gem_context_free(struct i915_gem_context *ctx)
for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++) {
struct intel_context *ce = &ctx->__engine[n];
+ struct intel_engine_cs *engine = ctx->i915->engine[n];
- if (ce->ops)
+ if (ce->ops) {
+ if (ctx->i915->contexts.free_hook)
+ ctx->i915->contexts.free_hook(ctx, engine);
ce->ops->destroy(ce);
+ }
}
kfree(ctx->name);
@@ -266,6 +266,9 @@ static inline bool need_preempt(const struct intel_engine_cs *engine,
}
ce->lrc_desc = desc;
+
+ if (ctx->i915->contexts.update_hook)
+ ctx->i915->contexts.update_hook(ctx, engine);
}
static struct i915_priolist *
@@ -2722,6 +2725,7 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
struct intel_engine_cs *engine,
struct intel_context *ce)
{
+ struct drm_i915_private *i915 = engine->i915;
struct drm_i915_gem_object *ctx_obj;
struct i915_vma *vma;
uint32_t context_size;
@@ -2777,6 +2781,9 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
ce->sw_counter = engine->instance;
}
+ if (i915->contexts.alloc_hook)
+ i915->contexts.alloc_hook(ctx, engine);
+
return 0;
error_ring_free:
In upcoming GuC patch we will require notification per engine context allocation/update/free to correctly setup GuC stage descriptors. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tomasz Lis <tomasz.lis@intel.com> Cc: Michal Winiarski <michal.winiarski@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 11 +++++++++++ drivers/gpu/drm/i915/i915_gem_context.c | 6 +++++- drivers/gpu/drm/i915/intel_lrc.c | 7 +++++++ 3 files changed, 23 insertions(+), 1 deletion(-)