From patchwork Wed Aug 29 19:18:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10580801 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EE6F514E1 for ; Wed, 29 Aug 2018 19:18:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E0A272B93B for ; Wed, 29 Aug 2018 19:18:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D4DFE2B96C; Wed, 29 Aug 2018 19:18:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 792C02B943 for ; Wed, 29 Aug 2018 19:18:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C235D6E5D4; Wed, 29 Aug 2018 19:18:42 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 11BE06E5D4 for ; Wed, 29 Aug 2018 19:18:33 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Aug 2018 12:18:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,304,1531810800"; d="scan'208";a="69099959" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga008.jf.intel.com with ESMTP; 29 Aug 2018 12:18:31 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [172.28.181.6]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id w7TJIOJa022844; Wed, 29 Aug 2018 20:18:30 +0100 From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Wed, 29 Aug 2018 19:18:09 +0000 Message-Id: <20180829191814.10872-5-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20180829191814.10872-1-michal.wajdeczko@intel.com> References: <20180829191056.63760-1-michal.wajdeczko@intel.com> <20180829191814.10872-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 14/21] drm/i915/guc: New reset-engine command X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Format of the ENGINE_RESET H2G message has been updated. Additionally, the firmware will send a G2H ENGINE_RESET_COMPLETE message (with the engine's guc_class in data[2]) to confirm that the reset has been completed (but this will be handled in a other patch). Requires GuC fw v25.161+. Credits-to: Michel Thierry Signed-off-by: Michal Wajdeczko Cc: Michel Thierry Cc: Daniele Ceraolo Spurio Cc: Vinay Belgaumkar Cc: Michal Winiarski Cc: Tomasz Lis --- drivers/gpu/drm/i915/intel_guc.c | 73 ++++++++++++++++++++++++++++++++++------ drivers/gpu/drm/i915/intel_guc.h | 6 ++++ 2 files changed, 69 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index a9c2f7b..64f1dca 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -576,27 +576,80 @@ int intel_guc_suspend(struct intel_guc *guc) return intel_guc_send(guc, data, ARRAY_SIZE(data)); } +static inline void +guc_set_class_under_reset(struct intel_guc *guc, unsigned int guc_class) +{ + GEM_BUG_ON(guc_class >= GUC_MAX_ENGINE_CLASSES); + bitmap32_set_bit(&guc->engine_class_under_reset, guc_class); +} + +static inline void +guc_clear_class_under_reset(struct intel_guc *guc, unsigned int guc_class) +{ + GEM_BUG_ON(guc_class >= GUC_MAX_ENGINE_CLASSES); + bitmap32_clear_bit(&guc->engine_class_under_reset, guc_class); +} + +static inline bool +guc_is_class_under_reset(struct intel_guc *guc, unsigned int guc_class) +{ + return bitmap32_test_bit(&guc->engine_class_under_reset, guc_class); +} + +static int __guc_action_reset_engine(struct intel_guc *guc, + u32 guc_class, + u32 stage_id) +{ + u32 action[] = { + INTEL_GUC_ACTION_REQUEST_ENGINE_RESET, + guc_class, + stage_id, + }; + + return intel_guc_send(guc, action, ARRAY_SIZE(action)); +} + +#define GUC_ENGINE_RESET_COMPLETE_WAIT_MS 100 + /** * intel_guc_reset_engine() - ask GuC to reset an engine * @guc: intel_guc structure * @engine: engine to be reset + * + * Ask GuC to reset an engine. The firmware will send a separate + * ENGINE_RESET_COMPLETE message (with the engine's guc_class) + * to confirm that the reset has been completed. */ int intel_guc_reset_engine(struct intel_guc *guc, struct intel_engine_cs *engine) { - u32 data[7]; + struct intel_guc_client *client = guc->execbuf_client; + u32 guc_class = engine->guc_class; + int ret; - GEM_BUG_ON(!guc->execbuf_client); + GEM_BUG_ON(guc_is_class_under_reset(guc, guc_class)); + guc_set_class_under_reset(guc, guc_class); - data[0] = INTEL_GUC_ACTION_REQUEST_ENGINE_RESET; - data[1] = engine->guc_id; - data[2] = 0; - data[3] = 0; - data[4] = 0; - data[5] = guc->execbuf_client->stage_id; - data[6] = intel_guc_ggtt_offset(guc, guc->shared_data); + ret = __guc_action_reset_engine(guc, guc_class, client->stage_id); + if (ret) + goto out; - return intel_guc_send(guc, data, ARRAY_SIZE(data)); + if ((wait_for(!guc_is_class_under_reset(guc, guc_class), + GUC_ENGINE_RESET_COMPLETE_WAIT_MS))) { + DRM_ERROR("reset_complete timed out, engine class %d\n", + engine->guc_class); + ret = -ETIMEDOUT; + } + +out: + /* + * Clear flag on any failure, we fall back to full reset in + * case of timeout/error. + */ + if (ret) + guc_clear_class_under_reset(guc, guc_class); + + return ret; } /** diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index ad42faf..8688edc 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -74,6 +74,12 @@ struct intel_guc { /* Cyclic counter mod pagesize */ u32 db_cacheline; + /* + * Track outstanding request-engine-reset h2g commands, + * accessed by set/clear/is_engine_class_under_reset + */ + u32 engine_class_under_reset; + /* GuC's FW specific registers used in MMIO send */ struct { u32 base;